CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 501

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Power Management Controller Register Descriptions
6.18.2.6 General Purpose Events Status 0 (PM_GPE0_STS)
ACPI I/O Offset
Type
Reset Value
PM_GPE0_STS is the Status register for General Purpose Events. Status events are cleared by writing a 1 to the
appropriate FLAG bit. Writing 0 has no effect. By convention, bits [23:0] are associated with the Working domain while bits
[31:24] are associated with Standby domain. During Standby, bits [23:0] are unconditionally cleared. These events are all
individually enabled and then ORed together to form the System Control Interrupt (SCI).
AMD Geode™ CS5535 Companion Device Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
29:22
Bit
31
30
21
20
19
18
17
Name
GPIOM7_PME_
FLAG
GPIOM6_PME_
FLAG
RSVD
GPIOM5_PME_
FLAG
GPIOM4_PME_
FLAG
GPIOM3_PME_
FLAG
GPIOM2_PME_
FLAG
GPIOM1_PME_
FLAG
18h
R/W
00000000h
RSVD
Description
GPIO IRQ/PME Mapper Bit 7 PME Flag. If high, this bit records that a PME occurred
via bit 7 of the GPIO IRQ/PME mapper. Both this bit and the corresponding enable bit
in
passed on to the system. Write 1 to clear; writing 0 has no effect.
GPIO IRQ/PME Mapper Bit 6 PME Flag. If high, this bit records that a PME occurred
via bit 6 of the GPIO IRQ/PME mapper. Both this bit and the corresponding enable bit
in
passed on to the system. Write 1 to clear; writing 0 has no effect.
Reserved. Reads return 0; writes have no effect
GPIO IRQ/PME Mapper Bit 5 PME Flag. If high, this bit records that a PME occurred
via bit 5 of the GPIO IRQ/PME mapper. Both this bit and the corresponding enable bit
in
passed on to the system. Write 1 to clear, writing 0 has no effect.
GPIO IRQ/PME Mapper Bit 4 PME Flag. If high, this bit records that a PME occurred
via bit 4 of the GPIO IRQ/PME mapper. Both this bit and the corresponding enable bit
in
passed on to the system. Write 1 to clear; writing 0 has no effect.
GPIO IRQ/PME Mapper Bit 3 PME Flag. If high, this bit records that a PME occurred
via bit 3 of the GPIO IRQ/PME mapper. Both this bit and the corresponding enable bit
in
passed on to the system. Write 1 to clear; writing 0 has no effect.
GPIO IRQ/PME Mapper Bit 2 PME Flag. If high, this bit records that a PME occurred
via bit 2 of the GPIO IRQ/PME mapper. Both this bit and the corresponding enable bit
in
passed on to the system. Write 1 to clear; writing 0 has no effect.
GPIO IRQ/PME Mapper Bit 1 PME Flag. If high, this bit records that a PME occurred
via bit 1 of the GPIO IRQ/PME mapper. Both this bit and the corresponding enable bit
in
passed on to the system. Write 1 to clear; writing 0 has no effect.
PM_GPE0_EN
PM_GPE0_EN
PM_GPE0_EN
PM_GPE0_EN
PM_GPE0_EN
PM_GPE0_EN
PM_GPE0_EN
PM_GPE0_STS Bit Descriptions
PM_GPE0_STS Register Map
(ACPI I/O Offset 1Ch[31]) must be high in order for this PME to be
(ACPI I/O Offset 1Ch[30]) must be high in order for this PME to be
(ACPI I/O Offset 1Ch[21]) must be high in order for this PME to be
(ACPI I/O Offset 1Ch[20]) must be high in order for this PME to be
(ACPI I/O Offset 1Ch[19]) must be high in order for this PME to be
(ACPI I/O Offset 1Ch[18]) must be high in order for this PME to be
(ACPI I/O Offset 1Ch[17]) must be high in order for this PME to be
RSVD
9
8
31506B
7
6
5
4
3
2
1
501
0