CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 505

no-image

CS5535-UDCF

Manufacturer Part Number
CS5535-UDCF
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of CS5535-UDCF

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS5535-UDCF
Manufacturer:
AMD
Quantity:
20 000
Part Number:
CS5535-UDCF
Manufacturer:
AMD
Quantity:
13 069
Power Management Controller Register Descriptions
6.18.3.2 PM Sleep Control X Assert Delay and Enable (PM_SCXA)
PMS I/O Offset
Type
Reset Value
Reads always return the value written.
6.18.3.3 PM Sleep Control Y Assert Delay and Enable (PM_SCYA)
PMS I/O Offset
Type
Reset Value
Reads always return the value written.
AMD Geode™ CS5535 Companion Device Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
29:0
29:0
Bit
Bit
31
30
31
30
Name
RSVD
SLPX_EN
SLPX_DELAY
Name
RSVD
SLPY_EN
SLPY_DELAY
04h
R/W
00000000h
08h
R/W
00000000h
Description
Reserved. By convention write 0, but may write anything.
Sleep X Assert and Delay Enable. Must be high to assert the SLEEP_X ball and to
enable its assert delay specified in bits [29:0] (SLPX_DELAY).
Sleep X Assert Delay. Indicates the number of 3.57954 MHz clock edges to wait from
the assertion of SUSPA# before asserting the SLEEP_X ball. Bit 30 (SLPX_EN) must
be high to enable this delay.
SLEEP_X is not allowed to assert if this delay is larger than SLPCLK_DELAY (PMS
I/O Offset 10h[29:0]). This is only true if SLPCLK_EN is enabled (PMS I/O Offset
10h[30] = 1).
Description
Reserved. By convention write 0, but may write anything.
Sleep Y Assert and Delay Enable. Must be high to assert SLEEP_Y and enable its
assert delay specified in bits [29:0] (SLPY_DELAY).
Sleep Y Assert Delay. Indicates the number of 3.57954 MHz clock edges to wait from
the assertion of SUSPA# before asserting the SLEEP_Y ball. Bit 30 (SLPY_EN) must
be high to enable this delay.
SLEEP_Y is not allowed to assert if this delay is larger than SLPCLK_DELAY (PMS
I/O Offset 10h[29:0]). This is only true if SLPCLK_EN is enabled (PMS I/O Offset
10h[30] = 1).
PM_SCXA Bit Descriptions
PM_SCYA Bit Descriptions
PM_SCXA Register Map
PM_SCYA Register Map
SLPX_DELAY
SLPY_DELAY
9
9
8
8
31506B
7
7
6
6
5
5
4
4
3
3
2
2
1
1
505
0
0

Related parts for CS5535-UDCF