CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 508

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CS5535-UDCF

Manufacturer Part Number
CS5535-UDCF
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of CS5535-UDCF

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
CS5535-UDCF
Manufacturer:
AMD
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CS5535-UDCF
Manufacturer:
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Quantity:
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6.18.3.7 PM Sleep Control X De-assert Delay (PM_SCXD)
PMS I/O Offset
Type
Reset Value
Reads always return the value written.
508
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
29:0
29:0
Bit
31
30
Bit
31
30
Name
RSVD
SLPX_END_EN
SLPX_END_
DELAY
Name
RSVD
SLPEND_EN
SLPEND_DELAY
18h
R/W
00000000h
31506B
Description
Reserved. By convention write 0, but may write anything.
Sleep X De-assert and Delay Enable. Must be high to de-assert SLEEP_X and
enable the delay specified in bits [29:0] (SLPX_END_DELAY).
Sleep X De-assert Delay. Indicates the number of 3.57954 MHz clock edges to wait
from Sleep wakeup before de-asserting the SLEEP_X ball. Bit 30 (SLPX_END_EN)
must be high to enable this delay.
If PCI_IDE_IN_SLP is not enabled (PMS I/O Offset 20h[30] = 0) or is less than the
SLPX_END_DELAY, SLEEP_X de-asserts at the same time the PCI/IDE inputs are re-
enabled.
Description
Reserved. By convention write 0, but may write anything.
Sleep End Delay Enable. Must be high to enable the delay specified in bits [29:0]
(SLPEND_DELAY).
Sleep End Delay. Indicates the number of 3.57954 MHz clock edges to wait from
Sleep wakeup before de-asserting SUSP#. Bit 30 (SLPEND_EN) must be high to
enable this delay.
If PCI_IDE_IN_SLP is not enabled (PMS I/O Offset 20h[30] = 0) or the delay is less
than SLPEND_DELAY, SUSP# de-asserts at the same time the PCI/IDE inputs are re-
enabled.
PM_SCXD Bit Descriptions
PM_SED Bit Descriptions
PM_SCXD Register Map
SLPX_END_DELAY
AMD Geode™ CS5535 Companion Device Data Book
Power Management Controller Register Descriptions
9
8
7
6
5
4
3
2
1
0

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