CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 511

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Power Management Controller Register Descriptions
6.18.3.10 PM Working De-assert Delay and Enable (PM_WKD)
PMS I/O Offset
Type
Reset Value
Reads always return the value written, except for RSVD bits [29:20].
AMD Geode™ CS5535 Companion Device Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
29:20
19:0
Bit
31
30
Name
RSVD
WORKING_
DEASSERT_EN
RSVD
WORKING_
DEASSERT_
DELAY
30h
R/W
00000000h
RSVD
Description
Reserved. By convention write 0, but may write anything.
Working De-assert and Delay Enable. Must be high to de-assert the WORKING out-
put and to enable its delay specified in bits [19:0] (WORKING_DEASSERT_DELAY).
Use of this control implies a system sequence into the Standby state. The PMC dis-
ables its interfaces to non-Standby portions of the component and only considers
wakeup events from Standby circuits. The PMC also immediately asserts system reset
when SLP_CLK_EN# is asserted regardless of the value of
WORKING_DEASSERT_DELAY (bits [19:0]). Reset remains asserted throughout the
Standby state.
There is NOT an assert delay. The wakeup event causes the WORKING output to
assert. This event is called Standby wakeup.
On wakeup, Reset will continue to be applied to all non-Standby circuits for the length
of time specified in the RESET_DELAY (PMS I/O Offset 38h[19:0]).
Enabling this function and/or the function in PM_WKXD (PMS I/O Offset 34h[30] = 1)
causes the same Standby state events. Standby state is not entered unless
SLP_CLK_EN# is asserted.
Reserved. By convention write 0, but may write anything. Reads return 0.
Working De-assert Delay. Indicates the number of 32 kHz clock edges to wait from the
assertion of SLP_CLK_EN# before de-asserting the WORKING output. Bit 30
(WORKING_DEASSERT_EN) must be high to enable this delay.
PM_WKD Bit Descriptions
PM_WKD Register Map
WORKING_DEASSERT_DELAY
9
8
31506B
7
6
5
4
3
2
1
511
0