CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 514

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.18.3.14 PM Fail-Safe Delay and Enable (PM_FSD)
PMS I/O Offset
Type
Reset Value
Reads always return the value written, except for RSVD bits [29:20].
514
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
29:20
29:20
19:0
19:0
Bit
Bit
31
30
31
30
Name
WORK_AUX_
LOCK
WORK_AUX_EN
RSVD
WORK_AUX_
DELAY
Name
PWRBUT_LOCK
PWRBUT_EN
RSVD
PWRBUT_DELAY
40h
R/W
00000000h
31506B
RSVD
Description
Working Auxiliary Lock. After this bit is set, the value in this register can not be
changed until RESET_STAND# is applied.
Working Auxiliary Delay Enable. Must be high to enable the delay specified in bits
[19:0] (WORK_AUX_DELAY). If this bit is low, the WORK_AUX output is uncondition-
ally asserted at Standby wakeup. If WORK_AUX was not de-asserted going into
Standby, then this control is a “don’t care”.
Reserved. By convention write 0, but may write anything. Reads return 0.
Working Auxiliary Assert Delay. Indicates the number of 32 kHz clock edges to wait
from Standby wakeup before asserting the WORK_AUX output. Bit 30
(WORK_AUX_EN) must be high to enable this delay.
May be programmed to assert before or after RESET_OUT# de-asserts.
The Standby wakeup event is not recognized until Normal (NWKD) or Abnormal
(AWKD) to Work Delay expires, if those delays are enabled. (See PMS I/O Offset 4Ch
and 50h for details regarding the NWKD and AWKD registers.)
Description
Power Button Lock. After this bit is set, the value in this register can not be changed
until RESET_STAND# is applied.
Power Button Enable. Must be high to enable the fail-safe function.
Reserved. By convention write 0, but may write anything. Reads return 0.
Power Button Delay. If the Power Button (PWR_BUT#) input signal is asserted for
PWRBUT_DELAY number of 32 kHz clock edges, then unconditionally de-assert
WORKING and WORK_AUX to remove Working power. If PWR_BUT# is still asserted
at wakeup, hold in Standby state until de-asserted.
PWR_BUT# needs to be asserted for at least one 32 kHz clock edge for this function to
work properly. A less than one 32 kHz clock edge pulse on PWR_BUT# may not be
registered.
The delay restarts if PWR_BUT# de-asserts and then asserts again. If PWR_BUT# is
already asserted, the delay restarts anytime PWRBUT_DELAY (this field) is written.
PM_WKXA Bit Descriptions
PM_FSD Bit Descriptions
PM_FSD Register Map
AMD Geode™ CS5535 Companion Device Data Book
Power Management Controller Register Descriptions
PWRBUT_DELAY
9
8
7
6
5
4
3
2
1
0