CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 519

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Flash Controller Register Descriptions
6.19
The registers for the Flash Controller are divided into three
sets:
• Standard GeodeLink Device (GLD) MSRs (Shared with
• Flash Controller Specific MSRs
• Flash Controller Native Registers
The MSRs are accessed via the RDMSR and WRMSR pro-
cessor instructions. The MSR address is derived from the
perspective of the CPU Core. See Section 4.2 "MSR
Addressing" on page 59 for more details.
All MSRs are 64 bits, however, the Flash Controller Spe-
cific MSRs (summarized in Table 6-69) are called out as 32
bits. The Flash Controller treats writes to the upper 32 bits
(i.e., bits [63:32]) of the 64-bit MSRs as don’t cares and
always returns 0 on these bits.
The Native registers associated with the Flash Controller
are NAND configuration registers, summarized in Table 6-
70. The NAND native registers are 4-kbyte memory
mapped or 16-byte I/O mapped. The base address is
defined by LBAR in Diverse Device and can be located at
any 4-kbyte boundaries if it is memory mapped, any 16-
byte boundary if it is I/O mapped. The NAND Flash Con-
troller is a 32-bit wide device present in Diverse Device
without burst capability. To access the MSR registers in the
NAND Flash Controller, a 32-bit wide bus is used as the
LBus interface. For NAND Command/Address, data write
AMD Geode™ CS5535 Companion Device Data Book
5140001Ch
5140001Dh
51400018h
51400019h
5140001Ah
5140001Bh
DIVIL, see Section 6.6.1 on page 317.)
Address
MSR
Flash Controller Register Descriptions
Type
R/W
R/W
R/W
R/W
R/W
R/W
Register Name
NOR Flash Control (NORF_CTL)
NOR Flash Timing for Chip Selects 0 and 1 (NORTF_T01)
NOR Flash Timing for Chip Selects 2 and 3 (NORTF_T23)
NAND Flash Data Timing MSR (NANDF_DATA)
NAND Flash Control Timing (NANDF_CTL)
Flash Reserved (NANDF_RSVD)
Table 6-69. Flash Controller Specific MSRs Summary
and read modes, the NAND Flash Controller provides the
valid data on the least significant nibbles of the LBus data
ports.
There are no NOR control registers located in I/O or mem-
ory space. All NOR timing control functions are located in
the Flash Specific MSRs. Additionally, the Diverse Device
LBAR MSRs associates up to four chip selects for four
Flash devices (see Section 6.6.2.9 "Local BAR - Flash
Chip Select (DIVIL_LBAR_FLSH[x])" on page 332 bit
details).
• MSR_LBAR_FLSH0 (MSR 51400010h) for use with
• MSR_LBAR_FLSH1 (MSR 51400011h) for use with
• MSR_LBAR_FLSH2 (MSR 51400012h) for use with
• MSR_LBAR_FLSH3 (MSR 51400013h) for use with
After the MSR setup is complete, a NOR Flash device can
be associated with a block of system memory using up to
28 address bits (A[27:0]).
The reference column in the summary tables point to the
page where the register maps and bit descriptions are
listed.
FLASH_CS0#.
FLASH_CS1#.
FLASH_CS2#.
FLASH_CS3#.
31506B
00000000h
07770777h
07770777h
07770777h
00000777h
00000000h
Reset
Value
Reference
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