CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 521

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Flash Controller Register Descriptions
Note 1. If any CHK_IOCHRDY[x] bit (bits [7:4]) is high, and the corresponding Chip Select (FLASH_CS[x]#) is low, then
AMD Geode™ CS5535 Companion Device Data Book
31:8
Bit
7
6
5
4
3
2
1
0
signal FLASH_IOCHRDY is checked to determine when to de-assert the RE# or WE# strobe. The RE# or WE#
strobe pulse width will be the programmed value (MSR_NORTF_T01[22:20], MSR_NORTF_T01[6:4],
MSR_NORTF_T23[22:20] and MSR_NORTF_T23[6:4]
If no CHK_IOCHRDY[x] bit (bits [7:4]) is high, or if no CHK_IORDY[x] bit is high that has a corresponding active
(low) Chip Select (FLASH_CS[x]#), then signal FLASH_IOCHRDY is ignored and the NOR Controller’s WE# and
RE# strobe pulse widths will be the values programmed in the NOR MSR registers (MSR_NORTF_T01[22:20],
MSR_NORTF_T01[6:4], MSR_NORTF_T23[22:20] and MSR_NORTF_T23[6:4]
WE# and RE# in the NOR MSR registers is programmed as 0, then the NOR Controller’s WE# and RE# generation
will use 16 as the count value of NOR pulse width.
Name
RSVD
CHK_IOCHRDY3
(Note 1)
CHK_IOCHRDY2
(Note 1)
CHK_IOCHRDY1
(Note 1)
CHK_IOCHRDY0
(Note 1)
WE_CS3
WE_CS2
WE_CS1
WE_CS0
Description
Reserved
Check I/O Channel Ready 3. Check FLASH_IOCHRDY signal for NOR Chip Select #3
(FLASH_CS3#)
0: Ignore IOCHRDY signal. No wait states will be inserted.
1: Check IOCHRDY before finishing the chip select strobe pulse.
Check I/O Channel Ready 2. Check FLASH_IOCHRDY signal for NOR Chip Select #2
(FLASH_CS2#)
0: Ignore IOCHRDY signal. No wait states will be inserted.
1: Check IOCHRDY before finishing the chip select strobe pulse.
Check I/O Channel Ready 1. Check FLASH_IOCHRDY signal for NOR Chip Select #1
(FLASH_CS1#)
0: Ignore IOCHRDY signal. No wait states will be inserted.
1: Check IOCHRDY before finishing the chip select strobe pulse.
Check I/O Channel Ready 0. Check FLASH_IOCHRDY signal for NOR Chip Select #0
(FLASH_CS0#)
0: Ignore IOCHRDY signal. No wait states will be inserted.
1: Check IOCHRDY before finishing the chip select strobe pulse.
Write Enable for CS3#. Write Enable for NOR Chip Select #3 (FLASH_CS3#)
0: No write cycles go out to NOR Flash interface via CS3#.
1: Allow write cycles to go out to NOR Flash interface.
Write Enable for CS2#. Write Enable for NOR Chip Select #2 (FLASH_CS2#)
0: No write cycles go out to NOR Flash interface via CS2#.
1: Allow write cycles to go out to NOR Flash interface.
Write Enable for CS1#. Write Enable for NOR Chip Select #1 (FLASH_CS1#)
0: No write cycles go out to NOR Flash interface via CS1#.
1: Allow write cycles to go out to NOR Flash interface.
Write Enable for CS0#. Write Enable for NOR Chip Select #0 (FLASH_CS0#)
0: No write cycles go out to NOR Flash interface via CS0#.
1: Allow write cycles to go out to NOR Flash interface.
NORF_CTL Bit Descriptions
)
increased by at least two local bus clock (33 MHz) cycles.
).
In this case, if the pulse width of
31506B
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