CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 522

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.19.1.2 NOR Flash Timing MSRs
The NOR Flash controller is used for NOR Flash or GPCS. The timing is different from device to device, so separate timing
registers are used for each device.
NOR Flash Timing for Chip Selects 0 and 1 (NORTF_T01)
MSR Address
Type
Reset Value
Note 1. The valid range for the count values of setup time, and hold time in NOR MSR registers is 1 through 7 (Local Bus
522
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:27
26:24
22:20
18:16
15:11
10:8
Bit
6:4
2:0
23
19
7
3
RSVD
clock cycles or LPC clock cycles) when a General Purpose device is used (with NOR Controller). If signal
FLASH_IOCHRDY is not used by the General Purpose device, then the valid range for the count value of pulse
width in NOR MSR registers is 1 through 7 (Local Bus clock cycles or LPC clock cycles). If FLASH_IOCHRDY is
used by the General Purpose device, then the valid range for the count value of pulse width in NOR MSR registers
is 2 through 7 (Local Bus clock cycles or LPC clock cycles). In the case of NOR devices, as NOR Controller doesn’t
support the use of FLASH_IOCHRDY (explained in Section 5.18.2 "NOR Flash Controller/General Purpose Chip
Select" on page 186),the valid range for the count values of setup time, pulse width, and hold time in NOR MSR
registers is 1 through 7 (Local Bus clock cycles or LPC clock cycles).In the case of NOR Controller’s WE# and RE#
strobe pulse widths, if NOR Control MSR register bits[7:4] (CHKRDY[3:0]) are enabled (active high) in the case of
General Purpose devices then the generated pulse widths will be longer than programmed count value. If setup or
hold time in NOR MSR registers is programmed as 0, then the NOR Controller’s WE# and RE# generation will use
16 as the count value of NOR setup or hold time.
Name
RSVD
Th1 (Note 1)
RSVD
Tp1
RSVD
Ts1 (Note 1)
RSVD
Th0 (Note 1)
RSVD
Tp0
RSVD
Ts0 (Note 1)
51400019h
R/W
07770777h
31506B
tH1
Description
Reserved. Reads return value written.
Hold Time for NOR Chip Select 1. Hold from WE# or RE# rising edge to chip select.
Refer to Figure 5-58 "NOR Flash with Wait States Timing" on page 188.
Reserved. Reads return value written
Strobe Pulse Width for NOR Chip Select 1. RE# and WE# strobe pulse width. At the end
of the Tp, sample the IOCHRDY pin to see if a wait state is needed. Refer to Figure 5-58
"NOR Flash with Wait States Timing" on page 188.
Reserved. Reads return value written.
Setup Time for NOR Chip Select 1. Chip select to WE# or RE# falling edge setup time.
Refer to Figure 5-58 "NOR Flash with Wait States Timing" on page 188.
Reserved. Reads return value written.
Hold time for NOR Chip Select 0. Hold from WE# or RE# rising edge to chip select. Refer
to Figure 5-58 "NOR Flash with Wait States Timing" on page 188.
Reserved. Reads return value written.
Strobe Pulse Width for NOR Chip Select 0. RE# and WE# strobe pulse width. At the end
of the Tp, sample the IOCHRDY pin to see if a wait state is needed. Refer to Figure 5-58
"NOR Flash with Wait States Timing" on page 188.
Reserved. Reads return value written.
Setup Time for NOR Chip Select 0. Chip select to WE# or RE# falling edge setup time.
Refer to Figure 5-58 "NOR Flash with Wait States Timing" on page 188.
tP1
NORTF_T01 Bit Descriptions
NORTF_T01 Register Map
tS1
RSVD
AMD Geode™ CS5535 Companion Device Data Book
tH0
Flash Controller Register Descriptions
9
8
7
6
tP0
5
4
3
2
tS0
1
0