CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 524

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.19.1.3 NAND Flash Data Timing MSR (NANDF_DATA)
MSR Address
Type
Reset Value
Most NAND devices have similar timing. All NAND devices share the timing registers. The valid range for the count values
of setup time and hold time in NAND MSRs is 0 through 7 Local Bus clock (‘lb_c’) cycles or LPC clock (‘lpc_c’) cycles and
the valid range for the count values of pulse width in NAND MSRs is 1 through 7 Local Bus clock (‘lb_c’) cycles or LPC
clock (‘lpc_c’) cycles.
524
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:27
26:24
22:20
18:16
15:11
10:8
Bit
6:4
2:0
23
19
7
3
RSVD
Name
RSVD
tRH
RSVD
tRP
RSVD
tRS
RSVD
tWH
RSVD
tWP
RSVD
tWS
5140001Bh
R/W
07770777h
31506B
tRH
Description
Reserved. Reads return value written.
Data Read Hold Time. This timing is just for internal state machine; no external refer-
ence point. Can be set to 0 if the hold time is not needed. Range = 0h to 7h. Refer to
Figure 5-61 "NAND Data Timing with Wait States" on page 190.
Reserved. Reads return value written.
Data Read Pulse Width. The RE# active pulse width in data read phase. Range = 1h
to 7h. Refer to Figure 5-61 "NAND Data Timing with Wait States" on page 190.
Reserved. Reads return value written.
Data Read Setup Time. This timing is just for internal state machine; no external refer-
ence point. Can be set to 0 if the setup time is not needed. Range = 0h to 7h. Refer to
Figure 5-61 "NAND Data Timing with Wait States" on page 190.
Reserved. Reads return value written.
Data Write Hold Time. The hold time from WE# rising edge to I/O bus is turned off.
Range = 0h to 7h. Refer to Figure 5-61 "NAND Data Timing with Wait States" on page
190.
Reserved. Reads return value written.
Data Write Pulse Width. The WE# active pulse width in data write phase. Note that
the data byte is put on the I/O bus at the same time the WE# is asserted. Range = 1h to
7h. Refer to Figure 5-61 "NAND Data Timing with Wait States" on page 190.
Reserved. Reads return value written.
Data Write Setup Time. This timing is just for internal state machine; no external refer-
ence point. Can be set to 0 if the setup time is not needed. Range = 0h to 7h. Refer to
Figure 5-61 "NAND Data Timing with Wait States" on page 190.
tRP
NANDF_DATA Bit Descriptions
NANDF_DATA Register Map
tRS
RSVD
AMD Geode™ CS5535 Companion Device Data Book
tWH
Flash Controller Register Descriptions
9
8
7
6
tWP
5
4
3
2
tWS
1
0