CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 527

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Flash Controller Register Descriptions
6.19.2.3 NAND I/O (NAND_IO)
Flash Memory Offset Any Odd Address between 801h-80Fh
Flash I/O Offset
Type
Reset Value
6.19.2.4 NAND Status (NAND_STS)
Flash Memory Offset 810h
Flash I/O Offset
Type
Reset Value
AMD Geode™ CS5535 Companion Device Data Book
Bit
7:0
Bit
7:4
3
2
1
0
7
7
Name
IO
Name
RSVD (RO)
FLASH_RDY (RO)
CTLR_BUSY (RO)
CMD_COMP
DIST_ST
6
6
05h
R/W
00h
06h
R/W
0xh
RSVD
Description
I/O Register. Writing to this register triggers a command/address phase sub-cycle on
the NAND Flash interface. The data written to this register is put on the I/O bus during
the sub-cycle. It returns previous written value when read.
Note:
Description
Reserved (Read Only). Returns 0 when read.
Flash Ready (Read Only). Double synchronized output (with respect to local bus
clock) of the NAND Flash device’s RDY/BUSY#.
NAND Controller Busy (Read Only). When high, indicates that the NAND Controller’s
state machines are busy.
NAND Command Complete. When high, indicates that the most recent NAND com-
mand has completed. May be read anytime. Write 1 to clear this bit. Writing 0 has no
effect.
NAND Distract Status. Occurrence of a NOR interruption during a NAND transaction
sets this bit. Write 1 to clear this bit. Writing 0 has no effect.
A NAND transaction is started as soon as CE# goes low. It is stopped when CE# goes
high. Typically, a NAND transaction needs multiple software commands (from 6 to
~500). Since the Flash Interface is shared between NAND and NOR Flash Controllers
and the NOR Flash Controller gets priority to use the Flash Interface, a NAND transac-
tion may be interrupted by a NOR transaction. DIST_ST bit is set to record this event.
NAND Flash software must take necessary actions to recover the uncompleted trans-
action.
5
5
Before writing to this register check for CTLR_BUSY bit (Flash Memory Offset
810h[2]/Flash I/O Offset 06h[2]) in NAND_STS register to be 0.
NAND_STS Bit Descriptions
NAND_IO Bit Descriptions
NAND_STS Register Map
NAND_IO Register Map
4
4
IO
FLASH_RDY
3
3
CTLR_BUSY
2
2
31506B
CMD_COMP
1
1
DIST_ST
0
0
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