CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 528

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.19.2.5 NAND ECC Control (NAND_ECC_CTL)
Flash Memory Offset 815h
Flash I/O Offset
Type
Reset Value
528
Bit
7:3
2
1
0
7
Name
RSVD
PARITY
CLRECC
ENECC
6
08h
R/W
04h
31506B
Description
Reserved. Reads return value written.
Parity.
0: ECC Parity registers are even parity.
1: ECC Parity registers are odd parity.
In the case of odd ECC parity, the value read from NAND_ECC_LSB (Flash Memory
Offset 811h/Flash I/O Offset 09h), NAND_ECC_MSB (Flash Memory Offset
812h/Flash I/O Offset 0Ah), and NAND_ECC_COL (Flash Memory Offset 813h/Flash
I/O Offset 0Bh) parity registers will be complement of the value written into these regis-
ters (except for LSB two bits of the NAND_ECC_COL register, they are always 11b for
odd parity).
Clear ECC Engine. Write 1 to clear ECC parity registers (NAND_ECC_LSB,
NAND_ECC_MSB, and NAND_ECC_COL), NAND Line Address Counter register
(NAND_LAC) and reset the ECC engine. Writing 0 has no effect.
The ECC engine contains an 8-bit Line Address Counter (LAC) to keep track of data
that has been read from or written into the NAND Flash. Software has to reset the
counter by writing a 1 to the CLRECC bit before transferring data to/from the NAND
Flash. Every data byte transferred to/from the NAND Flash Controller increments the
LAC. The NAND_LAC (Flash Memory Offset 814h/Flash I/O Offset 0Ch) register
reports the current count of the LAC.
Enable ECC Calculation Engine.
0: Disable ECC Engine. ECC engine holds previous value.
1: Enable ECC Engine. Every data byte transferred to/from the NAND Flash Controller
RSVD
will be counted in ECC calculation.
5
NAND_ECC_CTL Bit Descriptions
NAND_ECC_CTL Register Map
4
3
AMD Geode™ CS5535 Companion Device Data Book
PARITY
2
Flash Controller Register Descriptions
CLRECC
1
ENECC
0