CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 541

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ Control Processor Register Descriptions
6.20.2.9 GLCP Clock Mask for Debug Clock Stop Action (GLCP_CLKDISABLE)
MSR Address
Type
Reset Value
6.20.2.10 GLCP Clock Active Mask for Suspend Acknowledge (GLCP_CLK4ACK)
MSR Address
Type
Reset Value
This register has bits that correspond to the Clock Active (CLK_ACT) bits in GLCP_CLKACTIVE (MSR 51700011h). If the
bit in GLCP_CLK4ACK is set, then the SUSPA# signal will not go low unless all the marked clocks are inactive.
AMD Geode™ CS5535 Companion Device Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:34
63:0
33:0
Bit
Bit
Name
RSVD
CLKACT_EN_SLP
Name
RSVD
51700012h
R/W
00000000_00000000h
51700013h
R/W
00000000_00000000h
Description
Reserved
Clock Active Enable for Sleep. A 1 in any bit position indicates the corresponding
clock is to be monitored during a power management Sleep operation. When all the
clocks with associated 1s become inactive, the GLCP sends a Suspend Acknowledge
(SUSPA#) to the power management logic to begin the transition to the Sleep state. Use
of this register during Sleep sequences requires the CLK_DLY_EN bit (MSR
5170000Bh[1]) to be 0. For bit-to-clock correspondences and recommended operational
settings see Table 6-73 on page 536.
Description
Reserved. This register is reserved for internal testing only. These bits should not be
written to.
GLCP_CLKDISABLE Bit Descriptions
GLCP_CLKDISABLE Register Map
GLCP_CLK4ACK Bit Descriptions
GLCP_CLK4ACK Register Map
RSVD
RSVD
RSVD
9
9
8
8
31506B
7
7
6
6
5
5
4
4
3
3
2
2
1
1
541
0
0