CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 78

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

4.8.4
Each GeodeLink Device within the Geode CS5535 com-
panion device can generate errors. Furthermore, these
errors are controlled via the Standard GeodeLink Device
Error MSR (GLD_MSR_ERROR) located at MSR Address
3 within each GeodeLink Device. The register is organized
just like GLD_MSR_SMI, that is, the lower 32 bits contain
Enable (EN) bits, while the upper 32 bits contain Flag
(FLAG) bits (see Table 4-8 on page 74). The EN and FLAG
bits are organized in pairs of (n, n+32). For example:
(0,32); (1,33); (2,34); etc. The Error MSR is used to control
and report errors.
The SMI concepts of direct asynchronous and synchro-
nous carry over into similar error concepts. However, there
is no concept of an in-direct error. At each GeodeLink
Device, all of the Error FLAG bits are ORed together to
form the Error signal. The Error is routed through the GLIU
where it is ORed with all other device Errors to form the
Geode CS5535 companion device Error signal. This signal
is routed to the GLCP for debug purposes.
Only the GLIU is capable of generating synchronous errors
that utilize the Exception (EXCEP) bit of the associated
response packet. All other Geode CS5535 companion
device GeodeLink Devices only generate asynchronous
errors.
4.8.5
All the power management MSRs (GLD_MSR_PM) con-
form to the model illustrated in Table 4-10. The power and
I/O mode functions are completely independent other than
78
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
MODE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IO
H
MODE
MSR Address 3: Error Control
MSR Address 4: Power Management
IO
G
MODE
IO
F
31506B
MODE
IO
E
MODE
IO
D
Table 4-10. MSR Power Management Model
MODE
IO
C
MODE
IO
B
MODE
IO
A
sharing the same MSR. The GLD_MSR_PM fields have
the following definitions:
• Power Mode for Clock Domains:
• I/O Mode (Applies only to GLPCI_SB and ATAC
The PMC controls when the PCI/IDE inputs and outputs
(listed in Table 4-11 and Table 4-12) are asserted and de-
asserted. The PM_OUT_SLPCTL (PMS I/O Offset 0Ch)
and PM_IN_SLPCTL (PMS I/O Offset 20h) registers pro-
vide the global control of the PCI/IDE I/Os. The IO_MODE
bits individually control PCI (GLPCI_SB GLD_MSR_PM
(MSR 51000004h[49:48]) and IDE (ATAC GLD_MSR_PM
(MSR 51300004h[49:48]) I/Os.
— 00: Disable clock gating. Clocks are always on.
— 01: Enable active hardware clock gating. Clock goes
— 10: Reserved.
— 11: Reserved.
modules, see Table 4-11 and Table 4-12 for a list of
controlled signals):
— 00: No gating of I/O cells during a Sleep sequence
— 01: During a power management Sleep sequence,
— 10: During a power management Sleep sequence,
— 11: Immediately and unconditionally, force inputs to
off whenever this module’s circuits are not busy.
(Default).
force inputs to their non-asserted state when
PM_IN_SLPCTL is enabled.
force inputs to their non-asserted state when
PM_IN_SLPCTL is enabled, and park (force) outputs
low when PM_OUT_SLPCTL is enabled.
their not asserted state, and park (force) outputs low.
AMD Geode™ CS5535 Companion Device Data Book
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RSVD
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Global Concepts and Features
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