CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 87

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ PCI South Bridge
5.2.14
The CIS provides the system interface between the Geode
CS5535 companion device and Geode GX processor. The
interface supports several modes to send different combi-
nations of 16-bit side-band signals through the CIS signal
(ball P3). The sideband signals are synchronized to the
PCI clock through 2-stage latching. Whenever at least one
of 16 signals is changed, the serial transfer (using the PCI
clock) immediately starts to send the information from the
South Bridge to the North Bridge. But, if any bit changes
within 20 clocks of any previous change, the later change
will not be transmitted during the transfer. Another transfer
will start immediately after the conclusion of the transfer
due to the subsequent change.
There are three modes of operation for the CIS signal (ball
P3). Note that the transmitted polarity may be different than
the “generally defined” polarity state:
• Mode A - Non-serialized mode with CIS equivalent to
AMD Geode™ CS5535 Companion Device Data Book
Bit Position
0 (START)
1 (START)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 (END)
19 (END)
Note: Mode A is not listed since it is a non-serialized mode with CIS equivalent to SUSP# (reset mode).
SUSP# (reset mode). Not used in normal operation.
CPU Interface Serial (CIS)
Delayed Sleep#
Mode B
SUSP#
Sleep#
NMI#
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 5-3. CIS Serial Bits Assignment and Descriptions
Delayed Sleep#
Mode C
SUSP#
Sleep#
INTR#
NMI#
SMI#
1
1
1
1
1
1
1
1
1
1
0
0
1
1
Comment
Start Bit 0
Start Bit 1
Reserved
Reserved
Sleep Request
Non-Maskable Interrupt
Power Management Input Disable
Power Management Output Disable
Asynchronous SMI or Synchronous SMI
Maskable Interrupt out
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Stop Bit 0
Stop Bit 1
• Mode B - Serialized mode with signals SUSP#, NMI#,
• Mode C - Serialized mode with Mode B signals plus
If the GLPCI_MSR_CTRL bit HCD (MSR 51000010h[9]) is
set, any in-bound transaction, except in-bound memory
writes, will be held for any CIS transfer to complete before
claiming completion.
Mode selection is programmed in the GLPCI_MSR_CTRL,
bits [4:3] (MSR 51000010h).
Table 5-3 lists the serial data with corresponding side-band
signals. The serial shift register takes the selected side-
band signals as inputs. The signal SMI is the ORed result
of the SSMI_ASMI_FLAG (SSMI Received Event) bit in
GLPCI_SB GLD_MSR_SMI (MSR 51000002h[18]) and the
side-band signal ASMI. It also serves as a direct output to
the processor.
Sleep#, and Delayed Sleep#. Not used in normal opera-
tion.
SMI#, and INTR#. Used in normal operation.
31506B
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