CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 99

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

ATA-5 Controller
5.4
The hard disk controller is an ATA-5 compatible IDE con-
troller (ATAC). This controller supports UDMA/66, MDMA,
and PIO modes. The controller can support one channel
(two devices).
The IDE interface provides a variety of features to optimize
system performance, including 32-bit disk access, post
write buffers, bus master, MDMA, look-ahead read buffer,
and prefetch mechanism.
The IDE interface timing is completely programmable. Tim-
ing control covers the command active and recover pulse
widths, and command block register accesses. The IDE
data-transfer speed for each device on each channel can
be independently programmed allowing high-speed IDE
peripherals to coexist on the same channel as older, com-
patible devices. Faster devices must be ATA-5 compatible.
The ATAC also provides a software-accessible buffered
reset signal to the IDE drive. The IDE_RST# signal is
driven low during system reset and can be driven low or
high as needed for device power-off conditions.
Features include:
• ATA5-compliant IDE controller
• Supports PIO (mode 0 to 4), MDMA (mode 0 to 2), and
• Supports one channel, two devices
• Allows independent timing programming for each device
5.4.1
The IDE data port transaction latency consists of address
latency, asserted latency, and recovery latency. Address
latency occurs when a PCI master cycle targeting the IDE
data port is decoded, and the IDE_ADDR[2:0] and
IDE_CS# lines are not set up. Address latency provides
the setup time for the IDE_ADDR[2:0] and IDE_CS# lines
prior to IDE_IOR# and IDE_IOW#.
Asserted latency consists of the I/O command strobe
assertion length and recovery time. Recovery time is pro-
vided so that transactions may occur back-to-back on the
IDE interface without violating minimum cycle periods for
the IDE interface.
If IDE_IORDY is asserted when the initial sample point is
reached, no wait states are added to the command strobe
assertion length. If IDE_IORDY is negated when the initial
sample point is reached, additional wait states are added.
Recovery latency occurs after the IDE data port transac-
tions have completed. It provides hold time on the
IDE_ADDR[2:0] and IDE_CS# lines with respect to the
read and write strobes (IDE_IOR# and IDE_IOW#).
The PIO portion of the IDE registers is enabled through:
• Channel 0 Drive 0 PIO (ATAC_CH0D0_PIO) (MSR
AMD Geode™ CS5535 Companion Device Data Book
UDMA (mode 0 to 4)
51300020h)
ATA-5 Controller
PIO Modes
• Channel 0 Drive 1 PIO (ATAC_CH0D1_PIO) (MSR
The IDE channel and devices can be individually pro-
grammed to select the proper address setup time, asserted
time, and recovery time.
The bit formats for these registers are shown in Section
6.4.3 "ATAC Native Registers" on page 274. Note that
there are different bit formats for each of the PIO program-
ming registers depending on the operating format selected:
Format 0 or Format 1.
Channel 0 Drive 0/1 - The DMA register (MSR 51300021h/
51300023h) sets the format of the PIO register. If bit 31 =
0, Format 0 is used and it selects the slowest PIO mode
(bits [19:16]) for commands. If bit 31 = 1, Format 1 is used
and it allows independent control of command and data.
Also listed in the bit formats are recommended values for
the different PIO modes. Note that these values are only
recommended settings and are not 100% tested. Maximum
PIO data throughput is achieved when the PIO data port is
read/written using 32-bit accesses.
5.4.2
An IDE bus master is provided to perform the data trans-
fers for the IDE channel. The ATAC off-loads the CPU and
improves system performance.
The bus master mode programming interface is an exten-
sion of the standard IDE programming model. This means
that devices can always be dealt with using the standard
IDE programming model, with the master mode functional-
ity used when the appropriate driver and devices are
present. Master operation is designed to work with any IDE
device that supports DMA transfers on the IDE bus.
Devices that work in PIO mode can only use the standard
IDE programming model.
The IDE bus master uses a simple scatter/gather mecha-
nism, allowing large transfer blocks to be scattered to or
gathered from memory. This cuts down on the number of
interrupts to and interactions with the CPU.
5.4.2.1
Before the controller starts a master transfer it is given a
pointer to a Physical Region Descriptor Table. This pointer
sets the starting memory location of the Physical Region
Descriptors (PRDs). The PRDs describe the areas of mem-
ory that are used in the data transfer. The PRDs must be
aligned on a 4-byte boundary and the table cannot cross a
64 KB boundary in memory.
5.4.2.2
The IDE Bus Master registers have an IDE Bus Master
Command register and Bus Master Status register. These
registers can be accessed by byte, WORD, or DWORD.
51300022h)
Bus Master Mode
Physical Region Descriptor Table Address
IDE Bus Master Registers
31506B
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