MCIMX255AJM4A Freescale, MCIMX255AJM4A Datasheet - Page 80
MCIMX255AJM4A
Manufacturer Part Number
MCIMX255AJM4A
Description
Manufacturer
Freescale
Datasheet
1.MCIMX255AJM4A.pdf
(132 pages)
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Figure 53
Table 58
respectively the conditions and signals cited in
80
SCKT
SCKR
FST
HCKT
HCKR
No.
62
63
64
Symbol
i ck a
i ck s
x ck
i ck
Clock cycle
Clock high period
For internal clock
For external clock
Clock low period
For internal clock
For external clock
SCKR (output)
describes the general timing requirements for the ESAI module.
shows the ESAI HCKR timing diagram.
Signal Name
Internal clock
External clock
Internal clock, asynchronous mode
Internal clock, synchronous mode
4
HCKR
Characteristics
Significance
i.MX25 Applications Processor for Automotive Products, Rev. 4
1 2
Table 58. ESAI General Timing Requirements
Transmit clock
Receive clock
Transmit frame sync
Transmit high-frequency clock
Receive high-frequency clock
95
Table 56. ESAI Timing Conditions
Figure 53. ESAI HCKR Timing
Table 57. ESAI Signals
In the i.MX25, the internal clock frequency is equal to the IP bus frequency
(133 MHz)
The external clock may be derived from the CRM module or other external
clock sources
In asynchronous mode, SCKT and SCKR are different clocks
In synchronous mode, SCKT and SCKR are the same clock
Symbol
t
SSICC
—
—
—
—
—
Table
97
58.
Expression
2
2
4
4
2
2
T c
T c
—
T c
T c
T c
T c
Significance
9.0
9.0
3
Comments
Min.
30.0
30.0
15
15
Table 56
—
6
6
Max.
—
—
—
—
—
—
—
and
Freescale Semiconductor
Table 57
Condition
i ck
i ck
—
—
—
—
describe
Unit
ns
ns
ns