ALXD800EEXJ2VD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD C3 Datasheet - Page 451
ALXD800EEXJ2VD C3
Manufacturer Part Number
ALXD800EEXJ2VD C3
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.ALXD800EEXJ2VD_C3.pdf
(680 pages)
Specifications of ALXD800EEXJ2VD C3
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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Video Processor Register Descriptions
6.8.3.42 Video Coefficient RAM (VCR)
VP Memory Offset 1000h-1FFFh
Type
Reset Value
6.8.3.43 Panel Timing Register 1 (PT1)
VP Memory Offset 400h
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:48
47:32
31:16
63:32
15:0
Bit
Bit
31
30
VC3
VC2
VC1
VC0
Name
RSVD (RO)
RSVD
FP_VSYNC_
POL
Name
R/W
xxxxxxxx_xxxxxxxxh
R/W
00000000_00000000h
VC3
VC1
Description
Coefficient 3. Coefficient for tap 3 of filter.
Coefficient 2. Coefficient for tap 2 of filter.
Coefficient 1. Coefficient for tap 1 of filter.
Coefficient 0. Coefficient for tap 0 of filter.
Description
Reserved (Read Only). Reads back as 0.
Reserved. This bit is not defined.
FP_VSYNC Input Polarity. Selects positive or negative polarity of the FP_VSYNC input.
Program this bit to match the polarity of the incoming FP_VSYNC signal. Note that FP
Memory Offset 408h[23] controls the polarity of the output VSYNC.
0: FP_VSYNC is normally low, transitioning high during sync interval. (Default)
1: FP_VSYNC is normally high, transitioning low during sync interval
VCR Bit Descriptions
PT1 Bit Descriptions
VCR Register Map
PT1 Register Map
RSVD
RSVD
9
9
8
8
VC2
VC0
33234H
7
7
6
6
5
5
4
4
3
3
2
2
1
1
451
0
0
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