AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet
AMD-8132BLCT
Specifications of AMD-8132BLCT
Related parts for AMD-8132BLCT
AMD-8132BLCT Summary of contents
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... Overview The AMD-8132™ HyperTransport™ PCI-X supporting DDR transfer rates. The AMD-8132 tunnel is compliant with HyperTransport™ I/O Link Specification, Rev 2.0 including errata up to specification Rev 1.05c. The package millimeter, 829 ball, flip-chip organic BGA. The core is 1.2 volts. Power dissipation is 8 watts. ...
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... Trademarks AMD, the AMD Arrow logo, and combinations thereof, and AMD-8132 are trademarks of Advanced Micro Devices, Inc. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium. PCI registered trademark of the PCI-SIG Corporation. ...
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... Upstream Transactions 1.3.6.4 Downstream Transactions 1.3.7 Hot-Plug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.3.7.1 Multi-Slot Hot-Plug 1.3.7.2 Single-Slot Hot-Plug 1.3.7.3 TPS2340A Hot-Plug Power Controller 1.3.7.3.1 TPS2340A Serial Interface 1.3.7.3.2 TPS2340A Serial Data: Power Controllers to Tunnel AMD-8132™ HyperTransport™ PCI . . . . . . . . . . . .38 Table of Contents ® 2.0 Tunnel Data Sheet ...
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... JTAG Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.4 Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.5 Straps During Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.6 Pins With Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.7 AMD-8132™ Tunnel Configurations: Their Effect on Alternate Functions . . . . . . . . . . . . . . 57 2.7.1 Internal Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.7.1.1 Single Slot: Mode 2 2.7.1.2 Multiple Slots: Mode 1 ECC 2.7.1.3 Multiple Slots: Mode1 Without ECC 2 ...
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... Clock Control MSI Mapping Capability Block Header MSI Mapping Capability Block Lower Address MSI Mapping Capability Block Upper Address 3.3 PCI-X IOAPIC Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 IOAPIC Vendor and Device ID AMD-8132™ HyperTransport™ PCI . . . . . . .91 ...
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... AMD-8132™ HyperTransport™ PCI-X IOAPIC Status and Command IOAPIC Revision and Class Code IOAPIC Device BIST-Header-Latency-Cache IOAPIC Base Address Low IOAPIC Base Address High IOAPIC Device Subsystem ID and Subsystem Vendor ID Pointer to Capabilities Block IOAPIC Control HyperTransport Revision Capabilities Block 3.4 PHY Compensation Control ...
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... Master Aborts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 5.2.8 Target Aborts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5.2.9 Split Completion Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5.2.10 Unexpected Split Completions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 5.2.11 PCI/PCI-X Busy Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 5.3 AMD-8132 Tunnel Error Signaling Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 AMD-8132™ HyperTransport™ PCI .151 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 ...
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... AMD-8132™ HyperTransport™ PCI-X 5.3.1 HyperTransport Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.3.1.1 Sync Flood 5.3.1.2 Posted Write Data Errors 5.3.1.3 Error Responses 5.3.2 Fatal/Nonfatal Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.3.3 PCI/PCI-X Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 5.3.3.1 PERR# Assertion 5.3.3.2 Target Aborts 5.3.3.3 Split Completion Error Messages 5.3.3.4 Data Poisoning Chapter 6 Test ...
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... Rev. 3.07 July 2005 List of Figures Figure 1. AMD-8132™ Tunnel: Block Diagram ..........................................................................18 Figure 2. Link Buffer Diagram .....................................................................................................19 Figure 3. AMD-8132 Tunnel Interrupt Routing.............................................................................22 Figure 4. System Diagram: Multiple Hot-Plug Slots on a Bridge ................................................32 Figure 5. System Diagram: PME_L Signals .................................................................................33 Figure 6. System Diagram: M66EN Signals With TPS2340A .....................................................34 Figure 7 ...
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... Signal Isolation Groups...................................................................................................32 Table 3. Register Naming Conventions ........................................................................................66 Table 4. Memory Mapped Address Spaces...................................................................................67 Table 5. Register Attributes ..........................................................................................................67 Table 6. AMD-8132™ Tunnel Registers and Register Addresses ...............................................68 Table 7. SHPC Command Codes ................................................................................................138 Table 8. Mode 1 Bus Speed Encodings.......................................................................................138 Table 9. Mode 2 Bus Speed Encodings.......................................................................................138 Table 10. ...
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... Third public release. Updated the OPN on page 195. 3.02 04/2005 Second public release. Updates since Revision 3.00 are marked with revision bars. 3.0 03/2005 Initial public release. AMD-8132™ HyperTransport™ PCI-X Revision History ® 2.0 Tunnel Data Sheet 11 ...
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... AMD-8132™ HyperTransport™ PCI-X 12 ® 2.0 Tunnel Data Sheet Revision History 26792 Rev. 3.07 July 2005 ...
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... Rev. 3.07 July 2005 Preface This manual provides the technical specifications for the AMD-8132™ HyperTransport™ PCI-X Users of this document are expected to be familiar with current revs of the HyperTransport and PCI-X protocols. References and Resources HyperTransport™ I/O Link Specification, Rev 2.0 PCI-X Protocol Addendum to the PCI Local Bus Specification, Rev 2 ...
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... IOAPIC I/O Advanced Programmable Interrupt Controller. IRR Interrupt Request Register. IV Interrupt Vector. LI AMD-8132™ tunnel HyperTransport™ interface. This interface is the data/command transfer mechanism between the links and the bridges. LR[0,1] Link receive module. LT[0,1] Link transmit module. Link Connection between two HyperTransport™ devices. ...
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... Rev. 3.07 July 2005 Acronym/Term TPS* Combinatorial reference indicating both the TPS2340A and TPS2342 Texas Instru- ments hot-plug controllers. US Upstream, toward the host bridge. AMD-8132™ HyperTransport™ PCI-X Description Preface ® 2.0 Tunnel Data Sheet 15 ...
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... AMD-8132™ HyperTransport™ PCI-X 16 ® 2.0 Tunnel Data Sheet Preface 26792 Rev. 3.07 July 2005 ...
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... HyperTransport chain (the primary bus) and a PCI-X bus (the secondary bus). The AMD-8132 tunnel can be connected to the HyperTransport host device through either the side 0 or the side 1 HyperTransport link interface; this is the upstream link. The AMD-8132 tunnel can be attached directly to the host device, or there can be a chain of one or more additional HyperTransport tunnels between the upstream link and the host device ...
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... AMD-8132™ HyperTransport™ PCI-X Figure 1. AMD-8132™ Tunnel: Block Diagram In the Figure 1 block diagram: • ARB [B,A] - Internal arbiter for the PCI bus. • CFG [B,A] - Control and status registers for bridge [B,A]. • GCM - Link interface cycle manager. • GPI - Bridge functions between the HyperTransport primary bus and the PCI/PCI-X secondary buses, split into a bridge B and a bridge A. • ...
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... Rev. 3.07 July 2005 • TX PHY - HyperTransport link transmit physical layer. Figure 2 shows buffers in the AMD-8132 tunnel. Figure 2. Link Buffer Diagram Cmd Data LR0 CFF, PW Receive Path NP RSP LT0 Link 0 Transmit PW: Posted Write buffers. NP: Nonposted buffers. RSP: Response buffers. Cmd: Command buffers ...
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... Link Behavior After a cold or warm reset, the AMD-8132 tunnel initializes its base UnitID (see DevA:0xC0 in section 3. this point it responds to HyperTransport configuration accesses to device and passes any other HyperTransport commands on to the other link if the other HyperTransport link is active. Once the base UnitID register is initialized, the AMD-8132 tunnel responds to configuration accesses to this UnitID or this UnitID+1 ...
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... The external arbiter should not park the bus on this grant line. The non-preemptable request comes out on the signal [B,A]_GNT_L1. The non-preemptable grant from the external arbiter is driven to the AMD-8132 tunnel on the signal [B,A]_REQ_L1. If this bus is not enabled for hot-plug, the non- preemptable request/grant lines do not need to be implemented and this grant line should be pulled high. ...
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... AMD-8132™ HyperTransport™ PCI-X Figure 3. AMD-8132™ Tunnel Interrupt Routing B_NIOAIRQA B_NIOAIRQA NIOAIRQA NIOAIRQA A_NIOAIRQA A_NIOAIRQA B_NIOAIRQB B_NIOAIRQB NIOAIRQB NIOAIRQB A_NIOAIRQB A_NIOAIRQB B_NIOAIRQC B_NIOAIRQC NIOAIRQC NIOAIRQC A_NIOAIRQC A_NIOAIRQC B_NIOAIRQD B_NIOAIRQD NIOAIRQD NIOAIRQD A_NIOAIRQD A_NIOAIRQD HT Interrupt Packet HT Interrupt Packet HT Virtual Wire Packet ...
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... Virtual Wire INTx packets, as set up by the BIOS. IOAPIC-capable operating systems clear the mask bits resulting in interrupt request messages to the host. The NIOAIRQ[D:A]_L signals from all instances of the AMD-8132 tunnel on a platform can be connected together; respectively etc. These four nodes are expected to be passed to the system’s legacy interrupt controller to generate interrupts on behalf of the AMD-8132 tunnel bridges when IOAPIC interrupts are not supported. Typically for PCI interrupts, the redirection register (RDR ...
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... See section 3.7 for more about SHPC_INTR. See Chapter 5 for more about error reporting. 1.3.2.3 Message Signalled Interrupts (MSI/MSI-X) The AMD-8132 tunnel responds to MSIs (as specified in PCI Local Bus Specification, Rev 2.3, section 6.8) and MSI-Xs (as specified in PCI Local Bus Specification, Rev 3.0, section 6.8) with the following restriction imposed by HyperTransport: ...
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... For the targeted AMD-8132 tunnel bridge, the WriteChainEnable bit Dev[B,A]:0x40[31] must be set. • The data for all writes must have been received by the AMD-8132 tunnel internal buffers. A write whose data is still being transferred across the HyperTransport bus won't be chained. ...
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... When prefetching is enabled for a memory read request (Dev[B,A]:0x40[PFEN_L] asserted for the particular master and Dev[B,A]:0x4C[MRPFEN] asserted if the request is an MR), these rules are followed: • The AMD-8132 tunnel may contain between 0 and 8 cache lines of prefetched data for a memory read at one time. ...
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... If the master terminates a burst, all requested and unrequested prefetch data is discarded if Dev[B,A]:0x4C[DPDMD_L] is asserted for that master. • If the AMD-8132 tunnel terminates a burst because the required next data line was not acquired and if Dev[B,A]:0x4C[DPDTD] is asserted, all unrequested prefetch data for that request is discarded as it arrives ...
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... If the COMPAT bit is set in the transaction and DevA:0x48[COMPAT then per the HyperTransport link protocol the AMD-8132 tunnel never claims the transaction. Such transactions are automatically passed to the other side of the tunnel or master aborted if the AMD-8132 tunnel is at the end of the chain. 1.3.6 Transaction Considerations 1 ...
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... A or bridge B). • Upstream PCI-initiated memory writes which include no valid byte enables complete normally over the PCI bus. However, the transaction may be dropped by the AMD-8132 tunnel resulting in no corresponding HyperTransport link transactions. This does not apply to I/O transactions. ...
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... For a single-slot hot-plug implementation, the AMD-8132 tunnel provides the bus isolation function so only the TPS* hot-plug power controller and the power switches are required. Each bridge supports a maximum of 4 slots when hot- plug mode is enabled ...
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... A and bridge B. If the TPS2342 is used, a single hot-plug power controller can be shared by bridge A and bridge B. The AMD-8132 tunnel is connected to the power controller via a serial bus. If the TPS2340A is used, one serial interface supports the power controllers for bridge A and bridge B. If the TPS2342 is used, there are two serial interfaces - one for each bridge ...
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... A SHPC SHPC ® PCI-X Bridge B B Link Table 2 associates the hot-plug power controller isolation switch control signal with the AMD-8132 tunnel slot signals. Table 2. Signal Isolation Groups Power Controller Signal Slot Signals Isolated BUSENx_L [B,A]_ACK64L_ECC, [B,A]_AD[63:0], [B,A]_CBE_L[7:0], [B,A]_DEVSEL_L, [B,A]_FRAME_L, [B,A]_GNT_L[3:0], [B,A]_IRDY_L, ...
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... AMD-8132 tunnel. Isolation switch control is driven by CLKEN_L rather than BUSEN_L, unlike other PCI/PCI-X control signals hot-plug configuration, the AMD-8132 tunnel [B,A]_M66EN pin is configured as an open drain output driven low by the AMD-8132 tunnel determined that the bus is to run at 33 MHz (conventional PCI mode), as indicated in SHPC[B,A]:x10[MODE] ...
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... If the TPS2340A is used, software issues the SHPC[B,A]:14 Set Bus Segment Speed/Mode command which immediately places the appropriate state on [B,A]_M66EN out of the AMD-8132 tunnel the TPS2340A is used, software issues the SHPC[B,A]:14 Enable All Slots command which results in the assertion of CLKENx_L so [B,A]_M66EN out of the AMD-8132 tunnel is enabled to the slot. If the 34 ® ...
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... Slot Enable Command Sequence Notes: • Signal states are shown from the perspective of the pins of the AMD-8132 tunnel. The perspective from the slot is different due to the isolation switches controlled by CLKENx_L and BUSENx_L. • Most slot signals includes the signals controlled by BUSENx_L. ...
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... Single-slot hot-plug support is enabled for each bridge through strapping options on [B,A]_GNT_L4, as reflected in Dev[B,A]:0x40[SSS_L]. The AMD-8132 tunnel drives all slot signals low throughout the duration of a cold reset and continues until after the TPS* hot-plug power controller applies power to the adapter. The AMD-8132 tunnel interprets the SHPC commands to control the signals in the power only, slot enable, and slot disable sequences and to receive BUSEN_L and CLKEN_L output from the TPS* to control its bus signal state ...
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... This pin remains tri-stated until the SHPC enables the slot so the state provided by the card in the slot can be observed. This pin is driven low by the AMD-8132 tunnel if the bus is to run in 33 MHz conventional PCI mode. ...
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... TPS2340A hot-plug power controllers and update the AMD-8132 tunnel SHPC status registers accordingly. There are two different groups of serial interface signals. • Common serial signals are connections between the AMD-8132 tunnel and all TPS2340A hot-plug power controllers and are shared across both PCI/PCI-X bridges. These signals are: HPSIC, HPSIL_L, HPSOC, HPSOD, HPSOR_L. • ...
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... RESETx_L and [B,A]_HPSOLC_L for the rest of the signals. The data is shifted whenever there is a need to change the state of these signals, normally as a result of a command to SHPC[B,A]:14. Regardless of how many slots are actually attached to the bridge, the AMD-8132 tunnel shifts out four slots worth of data followed by pulses on [B,A]_HPSORLC_L and [B,A]_HPSOLC_L. HPSOD transitions after the falling edge of HPSOC ...
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... TPS2342 hot-plug power controllers. The hot-plug serial interface is also used to read status information from the TPS2342 hot-plug power controllers and update the AMD-8132 tunnel SHPC status registers accordingly. There are four serial interface signals for each serial interface bus: [B,A]_HP_LC, [B,A]_HP_SID, [B,A]_HP_SOD, [B,A]_HP_CLK ...
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... The data is shifted whenever there is a need to change the state of these signals, normally as a result of a command to SHPC[B,A]:14. Regardless of how many slots are actually attached to the bridge, the AMD-8132 tunnel shifts out four slots worth of data followed by pulses on [B,A]_HP_LC. 1.3.7.4.4 TPS2342 SHPC Interrupts, Events, And Errors Under the conditions described by SHPC[B,A]:20, the AMD-8132 tunnel may assert [B,A]_PIRQA_L, PME_L, or indicate a system error on the links ...
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... The PCI-X PHY used in the AMD-8132 tunnel maintains tight control of these parameters regardless of temperature, voltage, or process variation. The PCI-X PHY accomplishes this control using compensation circuitry. Each PCI bus has a ball connected to an external calibration resistor ...
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... Refers to signals that are weakly pulled up or down to indicate configuration Strapping Function information to the AMD-8132 tunnel. The AMD-8132 tunnel samples these pins at power-up to determine its internal configuration. These strapping functions are discussed in section 2.5. Chapter 2 AMD-8132™ HyperTransport™ PCI-X ® ...
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... AMD-8132™ HyperTransport™ PCI-X 2.1 HyperTransport™ Link Signals In the following table are signals associated with the HyperTransport links. In the signal names: • [1,0] refers to the two sides of the tunnel. • [H,L] refers to the positive and negative sides of differential pairs. ...
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... Connect all the _N differential inputs together through a resistor to VDD. • Leave the differential outputs unconnected. • If there are unused link signals on an active link (because the AMD-8132 tunnel is connected to a device with a reduced bit width), then the unused differential inputs should also be connected as above. ...
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... AMD-8132™ HyperTransport™ PCI-X Pin Name. Description [B,A]_CAL. PCI-X ® calibration pins. These pins should be attached to ground through a resistor, see section 1.3.8. Under no conditions, including JTAG boundary scan, should these pins be driven above 1.5 V. [B,A]_CBE_L[7:0], [B,A]_CBE_L5__AD48, [B,A]_CBE_L4__AD49, [B,A]_CBE_L[3:0]. PCI-X ® ...
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... Alternate Function: This signal has two alternate functions. In external arbiter mode PCI request output from the AMD-8132 tunnel. In single slot mode the IDSEL signal for the single external device. See section 2.6. [B,A]_GNT_L0. This signal is an input while PWROK is low (strapping function). At all other times this signal is a PCI grant output ...
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... AMD-8132™ HyperTransport™ PCI-X Pin Name. Description [B,A]_PCIXCAP. PCI-X ® frequency capabilities selection; used to determine the mode of the PCI bus. The state of this signal is captured during a cold reset at the rising edge of LDTRESET_L (see section 4.2.1). After LDTRESET_L is deasserted, the state of [B,A]_PCIXCAP is ignored ...
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... Single slot mode is not enabled for this bus: Dev[B,A]:0x40[SSS_L] is not asserted (low). Alternate Function: This signal has three alternate functions external arbiter mode PCI grant input to the AMD-8132 tunnel single slot non-hot-plug mode the VIOSEL output for a PCI-X Mode 2 capable power supply. ...
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... If this pin is pulled high at the rising edge of PWROK, the AMD-8132 tunnel is configured to interface to the TPS2340A. See section 2.5. • If this pin is pulled low at the rising edge of PWROK, the AMD-8132 tunnel is configured to interface to the TPS2342. See section 2.5. NIOAIRQ[ D]_L. Non-IOAPIC interrupt request outputs. Each of these signals require a weak pullup resistor to V33 ...
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... Miscellaneous Signals The following signals are sorted by pin name. Pin Name. Description [B,A]_PCLK[3].In single-slot mode, these pins are used as straps for AMD internal use and should be pulled high. CMPOVR. This pin is required to be tied low for normal operation. DIFFOUT_[H,L]. Reserved (should be left unconnected). ...
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... B_AD27_PAD, B_AD28_PAD, B_AD29_PAD, B_AD30_PAD, B_AD31_PAD B_CBE_L0_PAD, B_CBE_L1_PAD, B_CBE_L2_PAD, B_CBE_L3_PAD B_PCLK1_PAD B_RESET_L_PAD 2.3.1 JTAG Signals A standard JTAG controller is implemented in the AMD-8132 tunnel using the following signals sorted by pin name. Pin Name. Description TCK. JTAG test clock. TDI. JTAG test data input. TDO. JTAG test data output. ...
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... Power and Ground The following signals are sorted by pin name. Pin Name. Description PLL_VDDA[2:1]. Analog 3.3-volt power plane for PLLs in the core of the AMD-8132™ tunnel. Filtering this power plane from digital noise is required. V33. 3.3-volt power plane for I/O. VDD. 1.2-volt power plane for the core of the AMD-8132 tunnel. ...
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... Dev[B,A]:0x40[SSS_L]. For details, see Dev[B,A]:0x40, PCI-X Miscellaneous. [B,A]_PCLK[3] [B,A]_PCLK[3]. In single-slot mode, these pins are used as straps for AMD internal use and should be pulled high. [B,A]_REQ_L4 Dev[B,A]:0x48[HPEN]. For details, see Dev[B,A]:0x48, PCI-X and Pins Latched at Rising Edge of PWROK. ...
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... PCI-X ® IDSEL signal for slot 0. Note: The AMD-8132 tunnel is always device 0 on the secondary PCI bus. So, this IDSEL is asserted for configuration accesses to device 1 on the secondary PCI bus, corresponding to AD[17] in the type 0 configuration access. [B,A]_NP_REQ_L. If Dev[B,A]:0x48[EXTARB_L] is asserted (low), this signal is used as the non-preemptable REQ_L to the arbiter ...
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... AMD-8132™ HyperTransport™ PCI-X Pin Name Alternate Function. Description. [B,A]_PCLK[4] [B,A]_BUSEN_L. When Dev[B,A]:0x48[HPEN] and Dev[B,A]:0x40[SSS_L] are asserted, this is the BUSEN_L input. See section 1.3.7.2. VIO[B,A]_OVERRIDE_DELAY. When Dev[B,A]:0x48[HPEN] is not asserted and Dev[B,A]:0x40[SSS_L] is asserted (low), this is the VIO[B,A]_OVERRIDE_DELAY input. See section 7 ...
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... AMD-8132™ Tunnel Configurations: Their Effect on Alternate Functions The AMD-8132 tunnel can be used in several different configurations. The following tables show how the AMD-8132 tunnel signals are used in these configurations. The configuration choices are: • Whether a bus is using an internal arbiter or an external arbiter. ...
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... AMD-8132™ HyperTransport™ PCI-X A and B ® PCI-X Pin Name Single Slot Not Hot-Plug A_ECC2 A_ECC2 A_ECC3 A_ECC3 A_ECC4 A_ECC4 A_ECC5 A_ECC5 A_GNT_L0 A_GNT_L0 A_GNT_L1 A_IDSEL A_GNT_L4 -- A_PCLK1 A_VIOEN A_PCLK4 VIOA_OVERRIDE_DELAY A_BUSEN_L A_REQ_L0 A_REQ_L0 A_REQ_L1 A_VIOSEL A_REQ_L4 -- A_PCIXCAP A_PCIXCAP B_ECC2 B_ECC2 ...
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... A non-single-slot system capable of running in PCI-X Mode 1 with ECC must provide pullups on [B,A]_ECC[3:2] since these will be treated as PCI requests until the bus is configured in ECC mode three slots are supported if not in hot-plug mode two slots are supported in hot-plug mode. Chapter 2 AMD-8132™ HyperTransport™ PCI-X Signal Descriptions ® 2.0 Tunnel Data Sheet ...
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... AMD-8132™ HyperTransport™ PCI-X A and B ® PCI-X Mode 1 Pin Name Two or Three Slot Not Hot-Plug A_ECC2 A_ECC2 A_ECC3 A_ECC3 A_ECC4 A_ECC4 A_ECC5 A_ECC5 A_GNT_L0 A_GNT_L0 A_GNT_L1 A_GNT_L1 A_GNT_L4 A_GNT_L4 A_PCLK1 A_PCLK1 A_PCLK4 A_PCLK4 A_REQ_L0 A_REQ_L0 A_REQ_L1 A_REQ_L1 A_REQ_L4 A_REQ_L4 A_PCIXCAP ...
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... B_REQ_L0 B_REQ_L1 B_REQ_L1 B_REQ_L4 B_REQ_L4 B_PCIXCAP B_PCIXCAP HPSIC -- HPSIL_L -- HPSOC -- HPSOD -- Chapter 2 AMD-8132™ HyperTransport™ PCI-X A and B ® PCI, PCI-X PCI, PCI-X ® Multi-Slot Mode Multi-Slot Mode One or Two One or Two Hot-Plug TPS2340A Hot-Plug TPS2342 Per Bus A_REQ_L2 A_REQ_L2 A_REQ_L3 ...
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... AMD-8132™ HyperTransport™ PCI-X 2.7.2 External Arbiter 2.7.2.1 Single Slot Single slot PCI-X Mode 2 is not supported with an external arbiter. 62 ® 2.0 Tunnel Data Sheet Signal Descriptions 26792 Rev. 3.07 July 2005 Chapter 2 ...
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... B_P_GNT_L B_REQ_L1 B_NP_GNT_L B_REQ_L4 -- B_PCIXCAP B_PCIXCAP HPSIC -- HPSIL_L -- HPSOC -- HPSOD -- Chapter 2 AMD-8132™ HyperTransport™ PCI-X A and B Two Slot A and B Two Slot ® ® PCI-X Mode 1 PCI-X Mode 1 One or Two One or Two Hot-Plug TPS2340A Hot-Plug TPS2342 Per Bus Per Bus A_ECC2 ...
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... AMD-8132™ HyperTransport™ PCI-X 64 ® 2.0 Tunnel Data Sheet Signal Descriptions 26792 Rev. 3.07 July 2005 Chapter 2 ...
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... DevA:0x60 3.1.1 Configuration Space The address space for the AMD-8132 tunnel configuration registers is broken up into devices, functions, and offsets as defined by HyperTransport™ I/O Link Specification, Rev 2.0. The address space is accessed by HyperTransport-defined type 0 configuration or extended configuration cycles. The device number is mapped Chapter 3 AMD-8132™ ...
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... The function number is mapped into bits[10:8] of the configuration address. The offset is mapped to bits[7:0] of the configuration address. The address space for the AMD-8132 tunnel configuration space can be reached with either a HyperTransport type 0 access, or with an extended HyperTransport type 0 access. When using an extended type 0 access, all registers with an address above 255 bytes are reserved ...
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... Software can set the bit high by writing it. However, subsequent writes of 0 have no effect. LDTRESET_L must be asserted in order to clear the bit. Reserved For AMD internal use only. When reading Reserved bits, ignore the data. When writing to Reserved bits, preserve the data and merge it with the write; failure to do this results in undefined behavior. ...
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... AMD-8132™ HyperTransport™ PCI-X Table 6. AMD-8132™ Tunnel Registers and Register Addresses Register Name ® PCI-X Bridge Vendor and Device ID PCI-X Bridge Status and Command PCI-X Bridge Revision and Class Code PCI-X Bridge BIST-Header-Latency-Cache PCI-X SHPC Base Address Low PCI-X SHPC Base Address High ...
Page 69
... Rev. 3.07 July 2005 Table 6. AMD-8132™ Tunnel Registers and Register Addresses (Continued) Register Name Link Revision, Errors, and Frequency Capability 0 Feature, Link Errors, and Frequency Capability 1 Error Handling and Link Enumeration Link Non-Prefetchable Memory Space Extension Tunnel Control Clock Control ...
Page 70
... Default: 0010 0000h Bits Description 31 Detected Parity Error [DPE]. Read. Set by hardware. Write 1 to clear. Set if the AMD-8132™ tunnel accepts a HyperTransport™ read response or posted request with data error indicated. Note: This bit is cleared by PWROK reset but not by LDTRESET_L. 30 Signalled System Error [SSE]. Read. Set by hardware. Write 1 to clear. ...
Page 71
... Interrupt Status [INTSTATUS]. Read Only. Status of interrupts generated by the AMD-8132 tunnel. If this bit then the AMD-8132 tunnel has detected an SHPC interrupt, a fatal error nonfatal error, and is configured to drive this interrupt onto the [B,A]_PIRQA_L, [B,A]_PIRQB_L, or [B,A]_PIRQC_L interrupt pins respectively, unless gated by the interrupt disable bit [INTDISABLE]. ...
Page 72
... CLASSCODE. Provides the bridge class code as defined in PCI Local Bus Specification, Rev 2.3. Bits[3:1] of this field are zero. DevA:0x08[8] is the same as DevA:0x48[COMPAT]. DevB:0x08[8] is zero. 7:0 REVISION. AMD-8132™ tunnel revision— 01h = revision A1, 11h = revision B1, and 12h = revision B2. ® PCI-X Bridge BIST-Header-Latency-Cache ...
Page 73
... In conventional PCI mode, this functions per the PCI Local Bus Specification, Rev 2.3. • In PCI-X mode, the latency timer is not used when the AMD-8132 tunnel is the master of host- initiated transactions to the PCI-X bus. In PCI-X mode, the latency timer limits the number of clocks that the AMD-8132 tunnel owns the bus as the completer (master) only during split completions ...
Page 74
... Host-initiated transactions outside the windows are passed through the tunnel or master aborted if the AMD-8132 tunnel is at the end of a chain. • Secondary PCI-initiated transactions outside the windows are claimed by the AMD-8132 tunnel and passed to the host. For example: if IOBASE > IOLIM and Dev[B,A]:0x3C[VGAEN then no host-initiated I/O space transactions are forwarded to the secondary bus and all secondary PCI bus-initiated I/O space (not configuration) transactions are forwarded to the host. If MEMBASE > ...
Page 75
... Device Select Timing. Read Only. These bits are hardwired to indicate medium decoding speed. 24 Master Data Uncorrectable Error [MDPE]. Read. Set by hardware. Write 1 to clear The AMD-8132 tunnel sets this bit if Dev[B,A]:0x3C[PEREN] is set and one of these conditions occurs: • An uncorrectable error is detected during a data phase of a read. ...
Page 76
... AMD-8132™ HyperTransport™ PCI-X Dev[B,A]:0x20 Default: 0000 FFF0h Bits Description 31:20 Non-Prefetchable Memory Limit Address [MEMLIM]. Address bits[31:20]. See Dev[B,A]:0x[30:1C]. 19:16 Reserved. 15:4 Non-Prefetchable Memory Base Address [MEMBASE]. Address bits[31:20]. See Dev[B,A]:0x[30:1C]. 3:0 Reserved. Dev[B,A]:0x24 Default: 0001 FFF1h ...
Page 77
... The responses to nonposted requests that come from the host bus or secondary bus that result in master aborts indicate a target abort to the initiating bus (through PCI bus protocol or link protocol). Master aborts on PCI/PCI-X result in the assertion of Dev[B,A]:0x80[DISCARDED_POST]. Chapter 3 AMD-8132™ HyperTransport™ PCI-X ® mode. ® are silently dropped. ...
Page 78
... If Dev[B,A]:0x3C[VGA16DEC] is asserted, bits [15:10] are 0. If Dev[B,A]:0x3C[VGA16DEC] is clear, bits [15:10] are ignored in the decode. Bits [31:16] are 0. Secondary bus accesses to these ranges are not claimed by the AMD-8132 tunnel. 18 ISA Decoding Enable [ISAEN]. Read-Write. ...
Page 79
... AMD-8132 tunnel. 30 PCIMemWrBufMode. Read-Write. After reset deasserts, value = The AMD-8132™ tunnel will retry PCI Memory Writes if it does not have at least one internal buffer available The AMD-8132 tunnel will retry PCI Memory Writes to the lower half of a 64-byte HyperTransport™ ...
Page 80
... The PCLK signal is enabled to toggle. 15 Reserved. 14 DIS64. Read-Write. If this bit the AMD-8132 tunnel only generates and responds to transactions on this PCI bus as a 32-bit device. The AMD-8132 tunnel never asserts [B,A]_REQ64_L in the address phase and never asserts [B,A]_ACK64_L while asserting [B,A]_DEVSEL_L. 13 DISPU. Read-Write. If this bit internal pullups on this PCI bus are disabled and external pullups must be provided ...
Page 81
... It is not expected that these bits will need to be set; the order in which read requests are delivered to destinations does not matter in most cases. For details see the SeqId definition in HyperTransport™ I/O Link Specification, Rev 2.0 3 Reserved. Note: Chapter 3 AMD-8132™ HyperTransport™ PCI-X Registers ® 2.0 Tunnel Data Sheet ® mode, . ...
Page 82
... If the bridge is in hot-plug mode as specified by Dev[B,A]:0x48[HPEN] and SSS_L is low, then the bridge supports a single hot-plug slot without external isolation switches. In this mode, external isolation switches between the AMD-8132 tunnel and the slot are not required and should not be used. See section 1.3.7. ...
Page 83
... Correctable Nonfatal Enable. Read-Write. When asserted, this bit causes the nonfatal error interrupt to be asserted whenever a correctable error (Dev[B,A]:0x70[ECC Error Corrected and Dev[B,A]:0x70[ECC Error Phase] is not 0) is detected on the PCI-X Chapter 3 AMD-8132™ HyperTransport™ PCI-X ® Mode 2, this is the number of idle cycles counted prior to ® ...
Page 84
... PCI/PCI-X ® arbiter. • When asserted, the arbiter grants the PCI/PCI-X bus to the AMD-8132 tunnel when there is no request asserted. • When deasserted, the bus remains granted to the last bus master when there is no request. • This bit has no effect in external arbiter mode, Dev[B,A]:0x48[EXTARB_L ...
Page 85
... PWROK Hot-plug mode is not enabled on this bridge Hot-plug mode is enabled on this bridge. See section 1.3.7. Note: This bit is not affected by LDTRESET_L. Chapter 3 AMD-8132™ HyperTransport™ PCI-X runs at 50 MHz instead of 66 MHz. Higher PCI-X speeds are ® Registers ® ...
Page 86
... Note: This bit only exists in DevA:0x48 and is reserved in DevB:0x48. This bit is not affected by LDTRESET_L. 0 Compatibility Bus [COMPAT]. Read-Write The AMD-8132 tunnel routes all host initiated accesses in which the link-defined compat bit is set to the secondary bus. The default state of this bit is latched off of A_COMPAT at the trailing edge of PWROK reset. ...
Page 87
... There are no new requests for prefetch data after the initial batch specified by IPF_MRM One new request for a cache line of prefetch data is sent to the host by the AMD-8132 tunnel when data from an earlier cache line is transferred to the requesting master over the PCI bus (as long as prefetching isn’ ...
Page 88
... Discard Unrequested Prefetch Data Upon Host Request [DPDH Host requests do not affect prefetching the AMD-8132 tunnel issues a host request to the PCI bus, then all unrequested prefetch data is discarded. The master is allowed to reconnect and transfer the requested prefetch data and then be disconnected. ...
Page 89
... PCI-X2 533 (Not Supported)ECC Fh PCI-X2 533 (Not Supported)ECC 21 Split Request Delayed [SRD]. Read Only. Hardwired low. The AMD-8132™ tunnel automatically limits the number of upstream link read requests to the number of downstream buffers available; so there is no reason to limit the number of ADQs in read requests it accepts. Default = 0 20 Split Completion Overrun [SCO] ...
Page 90
... Device ID Messages between the primary and secondary interfaces. 28:22 Reserved. 21 Split Request Delayed [SRD]. Read Only. Hardwired low. The AMD-8132™ tunnel automatically limits the number of downstream PCI-X so there is no reason to limit the number of ADQs in read requests it accepts. 20 Split Completion Overrun. Read Only. This bit is hardwired low; it has no meaning since the primary bus is not PCI-X ® ...
Page 91
... Upstream Split Transaction Commitment Limit [USTCL]. Read-Write. This register controls no hardware. The AMD-8132™ tunnel automatically limits the number of upstream HyperTransport™ link read requests to the number of downstream buffers available; so there is no reason to limit the number of ADQs in read requests it accepts. This field is required to be greater than or equal to Dev[B,A]:0x68[USTC] ...
Page 92
... AMD-8132™ HyperTransport™ PCI-X ® PCI-X ECC Control and Status This register displays primary interface information if the Select Secondary ECC Registers bit is cleared, and secondary interface information if the Select Secondary ECC Registers bit is set. Since the primary interface is not PCI-X, it will never receive an ECC error and these registers return 0s if the Select Secondary ECC Regis- ters bit is cleared ...
Page 93
... RegisterECC Error Phase 0 No error 1 First 32 bits of address 2 Second 32 bits of address 3 Attribute phase 4 32-bit data phase 5 64-bit data phase 6 Reserved 7 Reserved Note: This register is cleared by PWROK, not by LDTRESET_L. Chapter 3 AMD-8132™ HyperTransport™ PCI-X Registers ® 2.0 Tunnel Data Sheet 93 ...
Page 94
... AMD-8132™ HyperTransport™ PCI-X 3 Additional Uncorrectable ECC Error. Write 1 to clear. This bit is set if the bridge detects an uncorrectable ECC error while already indicating some other ECC error (i.e., the ECC Error Phase register is non-zero). Once set, this bit remains set until software writes this location. ...
Page 95
... Address register are 0. Registers that store information from the failing transaction always store information directly from the bus (uncorrected), even if error correction is possible. These registers are Read Only. Note: This register is cleared by PWROK, not by LDTRESET_L. Chapter 3 AMD-8132™ HyperTransport™ PCI-X Registers ® 2.0 Tunnel Data Sheet ...
Page 96
... DevB:0x80. Note: Reset by PWROK, not LDTRESET_L. 18 PCI Busy Time Out Error. Read. Reset the AMD-8132 tunnel PCI bridge and write 1 to clear. This bit is set if the AMD-8132 tunnel detects that the PCI-X asserted) for 49152 PCI clocks. Note: Reset by PWROK, not LDTRESET_L. ...
Page 97
... This bit is also used in the equations for the fatal and nonfatal interrupts. See DevA:0xDC and Chapter 5. Note: This bit is set whenever PERR_L is asserted regardless of whether the AMD-8132 tunnel or another device asserted it. Reset by PWROK, not LDTRESET_L. ...
Page 98
... PCI Busy Time Out Nonfatal Enable. When asserted, this bit causes nonfatal error interrupt assertion whenever the log bit Dev[B,A]:0x80[18] is set. Depending on how the secondary bus hangs, the AMD-8132 tunnel can be involved in the operation in such a way that the error log bit will be set but the system software interrupt cannot be issued from the AMD-8132 tunnel to the HyperTransport™ ...
Page 99
... Default: 0000 0000h Bits Description 31:0 SHPC Data Port [DATA]. Accesses to this port access the register of the SHPC[B,A]:XX register set indexed by Dev[B,A]:0x90[SELECT]. Chapter 3 AMD-8132™ HyperTransport™ PCI-X Registers ® 2.0 Tunnel Data Sheet Dev[B,A]:0x90 Attribute: See Below Dev[B,A]:0x94 ...
Page 100
... AMD-8132™ HyperTransport™ PCI-X Power Management Capabilities This register is reserved if Dev[B,A]:0x48[HPEN] is low. Default: 480A C001h Bits Description 31:27 PME Support [PMES]. Indicates PME_L support in device state D0 (system state S0) and device state D3 hot (system state S1 Support [D2S]. Indicates that D2 device power state is not supported. ...
Page 101
... Power State [PWRS]. Read-Write. Indicates the current power state of the function. 00b = D0. 11b = D3 hot. If software attempts to write unsupported state to this field (01b = D1 or 10b = D2), the write operation completes normally on the bus; however, the data is discarded and no state change occurs. Chapter 3 AMD-8132™ HyperTransport™ PCI-X Registers ® 2.0 Tunnel Data Sheet ...
Page 102
... The HyperTransport™ defined address range for extended configuration space is FE_0xxx_xxxx (Type 0) and FE_1xxx_xxxx (Type 1). There is a mechanism in the AMD-8132™ tunnel allowing this address range to be redefined to a different location. DevA:0xB4[10:0] redefines bits [39:29] of this address space. Bits [63:40] of the address space are still required and bit [28] still distinguishes between Type 0 and Type 1 ...
Page 103
... Note:This is the version of the HyperTransport capability block for device B. Default: A1: 8825 F408h, Bx: 8840 F408h Bits Description 31:24 Capability Type. Capability type is Revision ID. Chapter 3 AMD-8132™ HyperTransport™ PCI-X Registers ® 2.0 Tunnel Data Sheet Attribute: See Below DevB:0xC0 Attribute: Read Only ...
Page 104
... Drop On Uninitialized Link [DOUI]. Read-Write. This bit specifies the behavior of transactions that are sent to uninitialized links. For transactions that are received by the AMD-8132™ tunnel and forwarded to a side of the tunnel When DevA:0x[C4/C8][INITCPLT and ENDOCH] for that side of the tunnel are both low, transactions remain in buffers awaiting transmission indefinitely (waiting for INITCPLT to be set high) ...
Page 105
... L[1,0]_CTLOUT_[H,L]0 is held asserted during the initialization sequence that follows an LDTSTOP_L deassertion after L[1,0]_CTLIN_[H,L]0 is detected asserted least 16 bit times About 50 microseconds. Note: This bit is cleared by PWROK reset but not by LDTRESET_L. See section 4.2.1.2. Chapter 3 AMD-8132™ HyperTransport™ PCI-X DevA:0xC4 and DevA:0xC8 Registers ® 2.0 Tunnel Data Sheet Attribute: See Below ...
Page 106
... Note: This bit is cleared by PWROK reset but not by LDTRESET_L. AMD recommends that this bit be set high in single-processor systems and be set low in multi-processor systems. ...
Page 107
... REVISION. Read Only. Indicates to which rev of the HyperTransport™I/O Link Specification the AMD-8132™ tunnel is compliant. Note: Rev A1 of the AMD-8132 tunnel only indicates support for HyperTransport™I/O Link Specification, Rev 1.05. Feature, Link Errors, and Frequency Capability 1 Default: 007D 0012h ...
Page 108
... Reserved. 5 UnitId Reorder Disable. Read-Write. When set, for the purpose of ordering the AMD-8132™ tunnel will treat all packets as being from the same UnitId. When clear, the AMD-8132 tunnel is able to perform limited reordering among packets from different sources Bit Addressing. Read Only. The AMD-8132 tunnel supports 64-bit HyperTransport™ addresses. ...
Page 109
... CRCERR bits are asserted in either of the link control registers DevA:0xC4 or DevA:0xC8. 21 Response Error Fatal Enable. Read Only. Always 0. The AMD-8132 tunnel never reports response errors. 20 End of Chain Error Fatal Enable. Read-Write. When asserted, this bit causes fatal error interrupt assertion whenever the end of chain error bit is asserted in one of the link error registers DevA:0xCC or DevA:0xD0 ...
Page 110
... AMD-8132™ HyperTransport™ PCI-X 7:0 Non-Prefetchable Upper Memory Base [NPUMB]. This field provides bits[39:32] of the non- prefetchable memory space address base specified by Dev[B,A]:0x20[MEMBASE]. See Dev[B,A]:0x1C. Note: NPUML and NPUMB are both device A registers but they affect both device A and device B non- prefetchable memory ranges ...
Page 111
... Note: The default value is to stream for lower latency. In general, the bits should only get set when the link bandwidths on each side are mismatched. Chapter 3 AMD-8132™ HyperTransport™ PCI-X Registers ® 2.0 Tunnel Data Sheet 111 ...
Page 112
... No power reduction while LDTSTOP_L is asserted When LDTSTOP_L is asserted after a STOP_GRANT cycle in which the SMAF field matches the ICGSMAF bit that is asserted, then the AMD-8132™ tunnel power is reduced through gating of internal clocks. For example: if clock gating is required for SMAF values of 3 and 5, then ICGSMAF[3, 5] must be high ...
Page 113
... These registers are located in PCI configuration space: function 1 in the first device (device A) and function 1 in the second device (device B). • See section 3.1.2 for a description of the register naming convention. Chapter 3 AMD-8132™ HyperTransport™ PCI-X ® MSI/MSI-Xs are mapped to Registers ® ...
Page 114
... IOAPIC Vendor and Device ID Default: 7459 1022h Bits Description 31:16 Device ID. IOAPIC device ID is 7459. 15:0 Vendor ID. AMD’s vendor ID is 1022. IOAPIC Status and Command Default: 0200 0000h Bits Description 31:3 Read Only. These bits are fixed in their default state. ...
Page 115
... Default: A1: 0800 1001h, Bx: 0800 1011h Bits Description 31:8 CLASSCODE. Provides the IOAPIC class code. 7:0 REVISION. AMD-8132™ tunnel revision. 01h = revision Ax. 11h = revision B1. IOAPIC Device BIST-Header-Latency-Cache Default: 0000 0000h Bits Description 31:24 BIST. These bits are fixed at their default values. ...
Page 116
... AMD-8132™ HyperTransport™ PCI-X IOAPIC Base Address High Default: 0000 0000h Bits Description 31:0 IOAPIC Base Address Register [IOABAR] High. These bits specify address space bits [63:32] of the IOAPIC register set APIC[B,A]:XX. IOAPIC Device Subsystem ID and Subsystem Vendor ID Default: 0000 0000h ...
Page 117
... Revision ID. Indicates to which rev of the HyperTransport™I/O Link Specification the AMD-8132™ tunnel is compliant. Note: Rev A1 of the AMD-8132 tunnel only indicates support for HyperTransport™I/O Link Specification, Rev 1.05. 15:8 Capabilities Pointer. (0x00) All 0s indicates this is the last capability block for this device/function. ...
Page 118
... AMD-8132™ HyperTransport™ PCI-X 3.4 PHY Compensation Control ® PCI-X PHY Compensation Control Dev[B,A]:1x80 Horizontal Default: See individual fields. Bits Description 31 Reserved. 30 COMPOFFSETPADD. Read-Write. • Setting this bit causes COMPOFFSETP to be added to the result of the compensation averager. • Setting this bit to 0 causes COMPOFFSETP to be subtracted from the result of the compensation averager ...
Page 119
... The results of the averager are ignored. Default = value of CMPOVR pin at PWROK 23:0 Reserved. Note: Dev[B,A]:1x90 Horizontal Chapter 3 AMD-8132™ HyperTransport™ PCI-X Registers ® 2.0 Tunnel Data Sheet Attribute: See Below Attribute: See Below 119 ...
Page 120
... AMD-8132™ HyperTransport™ PCI-X Default: See individual fields. Bits Description 31:13 Reserved. 12 Reserved. 11 Reserved. 10 COMPOFFSETIADD. Read-Write. • Setting this bit causes COMPOFFSETI to be added to the result of the compensation averager. • Setting this bit to 0 causes COMPOFFSETI to be subtracted from the result of the compensation averager ...
Page 121
... A write to this CSR updates it with the written value. • A read from this CSR returns the most recently calculated TX1 result. Default = 0000000b Note: Set to its default value at the rising edge of PWROK and unaffected by LDTRESET_L. Chapter 3 AMD-8132™ HyperTransport™ PCI-X Dev[B,A]:1x[D8,D4,C8,C4,C0] Registers ® 2.0 Tunnel Data Sheet ...
Page 122
... AMD-8132™ HyperTransport™ PCI-X 14:13 Reserved. Note: 12:7 Reserved. Note: 6:0 TX0ADJ. For TX0, the actual adjustment value that gets applied according to the setting of TXADJMODE. Values written to this CSR do not take effect until a 1 has been written to TXUPDATE. • A write to this CSR updates it with the written value. ...
Page 123
... A write to this CSR updates it with the written value. • A read from this CSR returns the most recently calculated RX result. Default = 01000b Note: Set to its default value at the rising edge of PWROK and unaffected by LDTRESET_L. Chapter 3 AMD-8132™ HyperTransport™ PCI-X Registers ® 2.0 Tunnel Data Sheet 123 ...
Page 124
... AMD-8132™ HyperTransport™ PCI-X Dev[B,A]:1xD4 Default: See individual fields. This block of CSRs provides a mechanism where by the HyperTransport calibration block can be controlled solely by reading and writing CSRs and is active when the CSR HT_DIRECT is asserted. Bits Description 31 HT_DIRECT. • When asserted, the pins of the HyperTransport™ calibration block are controlled directly by the CSRs in the doubleword 1xD4. • ...
Page 125
... Performance Counters Performance Counters and Control The AMD-8132™ tunnel implements two performance counters, DevA:1x[A0,A4]. The counter DevA:1xA0 is controlled by register DevA:1xA8; the counter DevA:1xA4 is controlled by register DevA:1xAC. Both counters require the count enable bit DevA:1xA8[ start counting and otherwise work identically. The DevA:1xA4 counter also requires its own private enable bit DevA:1xAC[ start counting ...
Page 126
... AMD-8132™ HyperTransport™ PCI-X DevA:1x[A0,A4] Counter Default: See individual fields. Bits Description 31:0 • If Control[ these are counter bits[31:0]. The count wraps to zero after FFFF_FFFFh and sets the overflow bit Control[3]. A write to the counter writes bits [31:0] and always clears the overflow bit Control[3]. • ...
Page 127
... If Control[ and this bit is set to 0, counting disconnects is disabled. If Control[ and this bit is set to 1, counting disconnects is enabled. Controlled by Control[16:13]; takes precedence over Control[23:19]. Default = 0 Note: If Control[ this bit is affected by Control[22:21]. Chapter 3 AMD-8132™ HyperTransport™ PCI-X Registers ® 2.0 Tunnel Data Sheet 127 ...
Page 128
... AMD-8132™ HyperTransport™ PCI-X 17 Count Target Done / Count Retries. • If Control[ and this bit is set to 0, counting target done commands is disabled. If Control[ and this bit is set to 1, counting target done commands is enabled. Any combination of Control[17:10] can be set, the count will be the total for all operations selected. ...
Page 129
... If Control[ and this bit is set to 0, counting idle PCLKs (no FRAME/IRDY/TRDY) is disabled. If Control[ and this bit is set to 1, counting idle PCLKs (no FRAME/IRDY/TRDY) is enabled. Default = 0 Note: If Control[ this bit affects Control[17:10]. Chapter 3 AMD-8132™ HyperTransport™ PCI-X Registers ® 2.0 Tunnel Data Sheet ® ...
Page 130
... AMD-8132™ HyperTransport™ PCI-X 7 Tunnel Destination. • If Control[ and this bit is set to 0, counting operations whose destination is the far (other side of the chip) transmitter is disabled. If Control[ and this bit is set to 1, counting operations whose destination is the far (other side of the chip) transmitter is enabled. ...
Page 131
... Reads provide all four bytes regardless of the byte enables. Only bits 7:0 of APIC[B,A]:00 are used. The index written to APIC[B,A]:00 selects one from the following table. Chapter 3 AMD-8132™ HyperTransport™ PCI-X Counter1 Disabled Disabled Disabled ...
Page 132
... AMD-8132™ HyperTransport™ PCI-X APIC[B,A]: Description 00[7:0] 00h APIC ID Register. Bits[31:24] are Read-Write; they control no hardware. All other bits are reserved. 01h IOAPIC Version Register. Bits[31:24] are reserved. Bits[23:16] Maximum Redirection Entry are Read Only. This field contains the entry number (0 being the lowest) of the highest entry in the I/O redirection table ...
Page 133
... If this the interrupt is active low. • For the RDRs associated with [B,A]PIRQ[D,C,B,A]_L this bit applies to the polarity of the [B,A]PIRQ[D,C,B,A]_L pins as they enter the AMD-8132 tunnel. Normally, this bit is expected to be programmed for active low interrupts. This bit has no effect on the NIOAIRQ[D,C,B,A]_L pins. ...
Page 134
... AMD-8132™ HyperTransport™ PCI-X 3.7 SHPC Working Registers These registers are accessed through either indexed configuration space (see Dev[B,A]:0x90[SELECT] and Dev[B,A]:0x94[DATA]) or non-indexed memory space (see SHPC[B,A]:00). All accesses (reads or writes) to SHPC registers must fit within a 32-bit aligned block. Accesses that span multiple 32-bit blocks result in undefined behavior. • ...
Page 135
... Reserved. 26:16 Physical Slot Number [PSN]. Specifies the physical slot number of the device specified by SHPC[B,A]:0C[FDN]. 15:13 Reserved. Chapter 3 AMD-8132™ HyperTransport™ PCI-X ® 2.0. If [B,A]:0x48[SHPC_PI_1 then the write-once value written to Registers ® 2.0 Tunnel Data Sheet SHPC[B,A]:08 Attribute: Write Once ...
Page 136
... AMD-8132™ HyperTransport™ PCI-X 12:8 First Device Number [FDN]. Specifies the device number assigned to the first hot-plug slot on the secondary bridge bus. 7:5 Reserved. 4:0 Number Of Slots Implemented [NSI]. Specifies the number of hot-plug slots on the bridge. SHPC Secondary Bus Configuration ...
Page 137
... Target Slot [TGT]. Read-Write. Specifies the slot to which SHPC[B,A]:14[CMD] is applied for the Slot Operation command. 7:0 SHPC Command Code [CMD]. Read-Write. Specifies the SHPC command to be executed; see Table 7. SHPC Command Codes. Chapter 3 AMD-8132™ HyperTransport™ PCI-X Registers ® 2.0 Tunnel Data Sheet Attribute: See Below 137 ...
Page 138
... AMD-8132™ HyperTransport™ PCI-X Table 7. SHPC Command Codes Command Name Slot Operation Set Bus Segment Speed/Mode 1 0 Power Only All Slots Enable All Slots Set Bus Segment Speed/ Mode 2 0 Decodings for SHPC command code fields are : • Attention Indicator and Power Indicator specify LED states. 00b = No Change; 01b = On; 10b = Blink; ...
Page 139
... Slot status bits capable of generating interrupts are SHPC[B,A]:[30, 2C, 28, 24][CPC_STS, IPF_STS, ABP_STS, MRLSC_STS, CPF_STS]. The corresponding interrupt masks are SHPC[B,A]:[30, 2C, 28, 24][CP_IM, IPF_IM, AB_IM, MRLS_IM, CPF_IM]. 0 Command Complete Interrupt Pending [CC_IP SHPC[B,A]:20[CC_STS and SHPC[B,A]:20[CC_IM Chapter 3 AMD-8132™ HyperTransport™ PCI-X Error Data Transfer ® Mode Handling Rate ...
Page 140
... AMD-8132™ HyperTransport™ PCI-X SHPC SERR Locator Default: 0000 0000h Bits Description 31:5 Reserved. 4:1 Slot SERR Pending [SERRP[4:1]]. Each bit n of this field corresponds to slot slot status bit capable of generating SERR is set and the corresponding SERR mask is 0. Slot status bits capable of generating SERR are SHPC[B,A]:[30, 2C, 28, 24][MRLSC_STS, CPF_STS] ...
Page 141
... LSR[AB] transitions from Isolated Power Fault Status [IPF_STS]. Read. Set by hardware. Write 1 to clear. Set when LSR[PF] changes from while LSR[SS 10b (slot is not in the enabled state). Chapter 3 AMD-8132™ HyperTransport™ PCI-X SHPC[B,A]:[30,2C,28,24] Registers ® 2.0 Tunnel Data Sheet ...
Page 142
... AMD-8132™ HyperTransport™ PCI-X 16 Card Presence Change Status [CPC_STS]. Read. Set by hardware. Write 1 to clear. Set when LSR[PRSNT1_2] field changes value. 15 Reserved. 14:12 ® PCI-X Capability [PCI-X_CAP]. Read-Only. Reflects the current PCI-X These bits are not valid if the slot is empty. ...
Page 143
... PCLK at the AMD-8132 tunnel, and the rising edge of the clock as observed at the destination of the systemboard trace [B,A]_PLLCLKI at the AMD-8132 tunnel and [B, A]_PCLK at the external device, as shown in Figure 19. The AMD-8132 tunnel is so designed for the purposes of meeting AC timing requirements. If the PCLK flight time matches the PLL feedback flight time, then PCLK as observed at the destination is equivalent to the PCI-defined PCLK signal to the AMD-8132 tunnel ...
Page 144
... When the AMD-8132 tunnel detects the STOP_GRANT broadcast enabled for clock gating, it enables clock gating for the next assertion of LDTSTOP_L. While exiting the power-managed state, the system is required to broadcast a STPCLK deassertion message. The AMD-8132 tunnel uses this message to disable clock gating during LDTSTOP_L assertions. This is important because an LDTSTOP_L assertion is not guaranteed to occur after the STOP_GRANT broadcast is received ...
Page 145
... HyperTransport™ Reset And Initialization LDTRESET_L and PWROK are both required to be low while power planes to the AMD-8132 tunnel are invalid and for at least 1 millisecond after the power planes are valid. Deassertion of PWROK is a cold reset. After PWROK is brought high, LDTRESET_L is required to stay low for at least 1 additional millisecond. ...
Page 146
... AMD-8132™ HyperTransport™ PCI-X 6. The AMD-8132 tunnel starts observing the state of L[1,0]_CTLIN_[H,L]0 and waits for it to assert before starting the next step. 7. Based on the state of DevA:0x[C8:C4][EXTCTL], the AMD-8132 tunnel holds L[1,0]_CTLOUT_[H,L]0 asserted for either a minimum of 16 additional bit times, or for approximately 50 additional microseconds. ...
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... The Supported R/G/P column indicates the sets of REQ_L, GNT_L, and PCLK signals supported by the AMD-8132 tunnel bridge in that mode. There may be other constraints, such as electrical requirements, that further limit the number of external devices supported. For example, in PCI-X Mode 1 at 100 MHz, 5 slots will not work Chapter 4 AMD-8132™ ...
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... PCI cards properly initialize. • bridge from the AMD-8132 tunnel supports PCI-X Mode 2 operations, then there must be a single PCI/PCI-X slot. This slot must have the MODE2 pin asserted. SSS_L for this bridge must also be asserted (i.e., the AMD-8132 tunnel must know there is only one slot on this bus) ...
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... HyperTransport™ Interface Errors 5.1.1 Sync Flood Once its link receivers are initialized, if the AMD-8132 tunnel detects sync flooding in either link receiver, it propagates sync flooding out its active transmitters. No enables are required. No logging is performed. 5.1.2 CRC Errors HyperTransport CRC Errors are defined in HyperTransport™ I/O Link Specification, Rev 2.0, sections 10.1.1 and 10 ...
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... End of Chain (EOC) receive buffer overflow errors are defined in HyperTransport™ I/O Link Specification, Rev 2.0, section 10.1.5. If the AMD-8132 tunnel receives a packet from a HyperTransport link that the routing rules indicate forwarded to the far link, but the far transmitter is unable to transmit it, the packet is handled as an end of chain packet and dropped. Reasons for the transmitter to drop a packet are: • ...
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... Posted Write Data Errors If the AMD-8132 tunnel receives a posted write request with the data error bit set that targets either of the PCI/ PCI-X bridges, it sets the Dev[B,A]:0x04[31] Detected Parity Error bit in the Status CSR corresponding to that bridge. If the request targets the bus below the bridge (as opposed to an internal register) and the global DevA:0xDC[6] Downstream Post Data Error Disable bit is clear, the data issued on the destination bus is poisoned ...
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... SERR_L Assertion Whenever the AMD-8132 tunnel detects the assertion of [B,A]_SERR_L by any device on the PCI/PCI-X bus, or detects [B,A]_SHPC_SERR, it sets the Dev[B,A]:0x1C[30] Received System Error (RSE) bit. • RSE can be mapped to cause sync flooding by setting the Dev[B,A]:0x3C[17] System Error Enable (SERREN) bit in the Bridge Control CSR. • ...
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... Bursts Across Address Range Boundaries When the starting address of a PCI-X read burst indicates the AMD-8132 tunnel is the target, but the byte count carries the transaction across an address range boundary, the AMD-8132 tunnel splits the transaction and returns read data up to the boundary. It then issues a split completion error message of PCI-X Bridge Error (Class 1), Target Abort (index 01h) ...
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... Parity/ECC Errors Depending on bus mode, the AMD-8132 tunnel checks either parity or ECC on all address and attribute phases on the PCI/PCI-X bus and on all data for which it is the target. In ECC modes, single-bit ECC errors are considered correctable if the secondary Dev[B,A]:0x70[30] Disable Single-Bit-Error Correction bit in the PCI-X ECC Error Control and Status CSR is clear ...
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... Posted Write Data Phase Uncorrectable Errors If the AMD-8132 tunnel detects an uncorrectable error in a data phase of a posted write for which it is the target, it forwards the data to HyperTransport normally but indicates a posted write data error on the packet containing the bad data beat. The AMD-8132 tunnel also asserts [B,A]_PERR_L for the bad beat if [B,A]_PERR_L is enabled ...
Page 156
... AMD-8132 tunnel address decode and routing controls are configured to accept that request and send transmitter that is unable to take it, as described in section 5.1.5. In that case, the AMD-8132 tunnel does not assert [B,A]_DEVSEL_L, allowing the request to master abort on the PCI/PCI-X bus. No log bits are set. ...
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... Target Aborts If a target abort is received for a command issued onto the PCI/PCI-X bus by the AMD-8132 tunnel, the action taken depends on what the command was. If the command was a posted request, the AMD-8132 tunnel sets the Dev[B,A]:0x1C[28] Received Target Abort (RTA) bit in the Secondary Status CSR, and the Dev[B,A]:0x80[1] DISCARDED_POST bit in the Misc Bridge Errors CSR ...
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... The AMD-8132 tunnel does not assert DEVSEL# for PCI-X split completions containing its Device ID, unless the completion’s tag matches a request which the AMD-8132 tunnel has outstanding. Requests to the AMD-8132 tunnel Device ID which do not match any outstanding request tags are expected to master abort. However, no other checking is performed. A split completion to the AMD-8132 tunnel Device ID with a matching tag but of a type that doesn’ ...
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... Posted Write Data Errors The AMD-8132 tunnel signals a posted write data error by setting the Data Error bit in the posted WrSized packet. It also logs this fact by setting the Dev[B,A]:0x04[24] Master Data Uncorrectable Error (MDPE) bit in the PCI-X Bridge Status and Command CSR corresponding to the bridge the posted write came from, if the Dev[B,A]:0x04[6] Parity Error Response (PERSP) bit in the same register is set ...
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... Dev[B,A]:0x1C[27] Signalled Target Abort (STA) bit in the appropriate Secondary Status CSR. 5.3.3.4 Data Poisoning Based on bus mode and data width, the AMD-8132 tunnel is capable of appropriately poisoning data it returns to the PCI/PCI-X bus by driving bad parity or ECC as follows: • Parity, 32-bit: force bad PAR value on all data beats. ...
Page 161
... IDCODE. Read the device ID code associated with the AMD-8132 tunnel. 3. HIGHZ. Other than TDO, all outputs of the AMD-8132 tunnel are in the high-impedance state. 4. SAMPLE/PRELOAD. Allows the state of all inputs to the AMD-8132 tunnel to be sampled in the boundary-scan register cells and then read by scanning out the JTAG boundary-scan chain. This mode also allows new values to be scanned into the boundary scan chain for subsequent use by the EXTEST instruction ...
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... AMD-8132™ HyperTransport™ PCI-X 162 ® 2.0 Tunnel Data Sheet Test 26792 Rev. 3.07 July 2005 Chapter 6 ...
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... Table 13. Temperature Temperature Minimum T CASE T -65 C STORAGE 7.1.2 Operating Ranges The AMD-8132 tunnel is designed to provide functional operation if the voltage and temperature parameters are within the limits defined in the following table. Table 14. Operating Ranges Parameter Minimum Typical VDD 1.14 V33 3.135 VIO[B,A] Mode 1 3 ...
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... AMD-8132™ HyperTransport™ PCI-X Table 14. Operating Ranges (Continued) Parameter Minimum Typical VIO[B,A] Mode 2 VLDT 1.14 PLL_VDDA[1:2] 3.0 PLL_VDDA[1:2] Peak-To-Peak 7.1.3 Current and Power Consumption Table 15. DC Current and Power Consumption Power Plane PLL_VDDA1 (3.3 V) PLL_VDDA2 (3.3 V) V33 (3.3 V) VDD (1.2 V) VIOA • ...
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... PWROK. At the rising edge of PWROK, the AMD-8132 tunnel determines the operating mode of the PCI buses and drives [B,A]_VIOSEL accordingly. Thereafter, [B,A]_VIOEN is asserted. To ensure that the VIO[B,A] has stabilized, the AMD-8132 tunnel then waits an additional 100 milliseconds before de-asserting [B,A]_RESET_L. This 100 millisecond delay only occurs for buses capable of running in PCI-X Mode 2 and can be overridden at any point by asserting VIO[B,A]_OVERRIDE_DELAY (alternate function of [B,A]_PCLK[4]) ...
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... AMD-8132™ HyperTransport™ PCI-X The following figures are examples of legal power plane sequencing: Figure 20 for a system that is not Mode 2 capable; Figure 21 for a Mode 2 capable system. Figure 20. Example Sequence for A Not Mode 2 Capable System V3 PLL [B, Int Ext Notes: 1. V33, PLL_VDDA[2:1], VIO, VDD, and VLDT are power plane signals. ...
Page 167
... Input Requirements for REFCLK_[H,L] 7.2.1 REFCLK_[H,L]: DC Requirements Table 16. REFCLK_[H,L] DC Requirements Symbol Description V REFCLK_[H,L] input voltage high REFCLK_[H,L] input voltage low. IL Chapter 7 AMD-8132™ HyperTransport™ PCI ///////////////////// Minimum 0.2 -0.4 Electrical Data ® 2.0 Tunnel Data Sheet Maximum Units 0.4 V -0.2 V ...
Page 168
... R Output impedance differential. ON 7.2.3 Differential Clock Test Load A REFCLK_[H,L] clock source that meets the AMD-8132 tunnel signal requirements listed in Table 17 can be characterized using the differential test load shown in Figure 22. The single-ended measurement definitions are shown in Figure 23. 168 ® 2.0 Tunnel Data Sheet ...
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... Rev. 3.07 July 2005 Figure 22. Differential Test Load Figure 23. Single-Ended Measurement Definitions Chapter 7 AMD-8132™ HyperTransport™ PCI ohm Electrical Data ® 2.0 Tunnel Data Sheet ohms ohms pf 169 ...
Page 170
... AMD-8132™ HyperTransport™ PCI-X 7.3 3.3 Volt Signals 7.3.1 DC Characteristics: Signals on V33 Power Plane Table 18. V33: DC Signal Characteristics Symbol Description V Input voltage high Input voltage low Output voltage high Output voltage low Input leakage current Input capacitance. IN 7.3.2 AC Input Requirements: Signals on V33 Power Plane Table 19 ...
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... PCI and PCI-X See PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification, Rev 2.0a (or higher) for the electrical characteristics of PCI signals. Any deviation from this specification is listed in the AMD-8132™ ® HyperTransport™ PCI-X 2.0 Tunnel Revision Guide. ...
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... AMD-8132™ HyperTransport™ PCI-X 172 ® 2.0 Tunnel Data Sheet Electrical Data 26792 Rev. 3.07 July 2005 Chapter 7 ...
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... Rev. 3.07 July 2005 Chapter 8 Package and Pin Designations Figure 24. AMD-8132™ Tunnel: Ball Designations L0_CTLI L0_CADI L0_CADI VSS VSS VSS N_L0 N_L6 N_L4 B L0_COMP L0_CTLI L0_CADI L0_CADI L0_CADI L0_CADI NC _PD N_H0 N_L7 N_H6 N_L5 N_H4 C L0_COMP L0_CADI L0_CADI VSS ...
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... AMD-8132™ HyperTransport™ PCI-X The following tables sort the AMD-8132™ HyperTransport™ PCI-X sort signals by location. Table 32 - Table 41 sort signals by name. Table 22. Signals Sorted by Location Ball Signal Name A3 VSS A4 L0_CTLIN_L0 A5 VSS A6 L0_CADIN_L6 A7 VSS A8 L0_CADIN_L4 A9 VSS A10 L0_CADIN_L3 A11 VSS ...
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... VSS D20 L1_CLKOUT_H1 D21 VSS D22 L1_CADOUT_H13 D23 VSS D24 L1_CADOUT_H15 D25 VDD D26 VSS D27 VDD D28 L1_CTLIN_H0 D29 L1_CTLIN_L0 Chapter 8 AMD-8132™ HyperTransport™ PCI-X Ball Signal Name E1 VSS E2 L0_CADOUT_H7 E3 L0_CADOUT_L7 E4 VDD E5 DIFFOUT_L E6 L0_CADIN_H15 E7 L0_CADIN_L14 E8 L0_CADIN_H13 E9 L0_CADIN_L12 E10 L0_CLKIN_H1 ...
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... AMD-8132™ HyperTransport™ PCI-X Table 24. Signals Sorted by Location Ball Signal Name G1 VSS G2 L0_CADOUT_H5 G3 L0_CADOUT_L5 G4 VSS G5 L0_CADOUT_H14 G6 L0_CADOUT_L14 G7 VDD G8 VDDFB_H G9 VDD G10 VSS G11 VDD G12 VSS G13 VDD G14 VSS G15 VDD G16 VSS G17 VDD G18 VSS G19 VDD ...
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... VSS K20 VDD K21 VSS K22 VDD K23 VSS K24 VDD K25 L1_CLKIN_H1 K26 L1_CLKIN_L1 K27 VDD K28 L1_CADIN_H3 K29 L1_CADIN_L3 Chapter 8 AMD-8132™ HyperTransport™ PCI-X Ball Signal Name L1 VSS L2 L0_CADOUT_H2 L3 L0_CADOUT_L2 L4 VSS L5 L0_CADOUT_H11 L6 L0_CADOUT_L11 L7 VDD L8 VSS L9 VDD L10 VSS ...
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... AMD-8132™ HyperTransport™ PCI-X Table 26. Signals Sorted by Location Ball Signal Name N1 VSS N2 L0_CADOUT_H0 N3 L0_CADOUT_L0 N4 VSS N5 L0_CADOUT_H9 N6 L0_CADOUT_L9 N7 VDD N8 VSS N9 VDD N10 VSS N11 VDD N12 VSS N13 VDD N14 VSS N15 VDD N16 VSS N17 VDD N18 VSS N19 VDD ...
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... VSS T20 VDD T21 VSS T22 VDD T23 VSS T24 HPSOD T25 HPSIC T26 NIOAIRQD_L T27 V33 T28 V33 T29 V33 Chapter 8 AMD-8132™ HyperTransport™ PCI-X Ball Signal Name U1 TEST U2 TMS U3 TDO U4 TDI U5 VDDOK U6 PWROK U7 B_PLLCLKI U8 VSS U9 VIOB U10 VSS ...
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... AMD-8132™ HyperTransport™ PCI-X Table 28. Signals Sorted by Location Ball Signal Name W1 CMPOVR W2 B_PCIXCAP W3 B_PCLK3 W4 B_PCLK0 W5 B_AD32 W6 B_AD33 W7 B_AD47 W8 VSS W9 VIOB W10 VSS W11 VIOB W12 VSS W13 VIOB W14 VSS W15 VSS W16 VSS W17 VIOA W18 VSS W19 VIOA ...
Page 181
... VDD3FB_H AB22 VIOA AB23 A_AD16 AB24 A_AD17 AB25 A_AD30 AB26 A_AD31 AB27 A_GNT_L4 AB28 A_PIRQD_L AB29 A_REQ_L0 Chapter 8 AMD-8132™ HyperTransport™ PCI-X Ball Signal Name AC1 B_AD42 AC2 B_AD43 AC3 B_AD44 AC4 B_AD56 AC5 B_AD57 AC6 B_CBE_L5__AD48 AC7 B_AD50 AC8 ...
Page 182
... AMD-8132™ HyperTransport™ PCI-X Table 30. Signals Sorted by Location Ball Signal Name AE1 B_AD60 AE2 B_AD61 AE3 B_CBE_L6 AE4 B_CBE_L4__AD49 AE5 B_SERR_L AE6 B_IRDY_L AE7 B_AD9 AE8 B_AD11 AE9 B_CBE_L1 AE10 B_AD16 AE11 B_CBE_L2 AE12 B_AD31 AE13 B_ECC2 AE14 B_REQ_L1 AE15 ...
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... A_AD59 AH21 VSS AH22 A_PAR64__ECC7 AH23 A_DEVSEL_L AH24 VSS AH25 A_AD6 AH26 A_CBE_L1 AH27 VSS AH28 A_AD11 Chapter 8 AMD-8132™ HyperTransport™ PCI-X Ball Signal Name AJ3 B_REQ64_L__ECC6 AJ4 B_AD0 AJ5 B_AD2 AJ6 B_AD4 AJ7 B_AD7 AJ8 B_AD18 AJ9 B_AD21 AJ10 ...
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... AMD-8132™ HyperTransport™ PCI-X Table 32. Signals Sorted by Name A_A - A_M Pin Name Pin A_ACK64_L__ECC1 AC22 A_AD0 AD22 A_AD1 AE23 A_AD2 AE24 A_AD3 AG24 A_AD4 AE25 A_AD5 AF25 A_AD6 AH25 A_AD7 AG25 A_AD8 AG26 A_AD9 AJ27 A_AD10 AG27 A_AD11 AH28 A_AD12 ...
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... AJ24 A_STOP_L AJ25 A_TRDY_L AG23 B_ACK64_L__ECC1 AH4 B_AD0 AJ4 B_AD1 AG5 B_AD2 AJ5 B_AD3 AG6 B_AD4 AJ6 Chapter 8 AMD-8132™ HyperTransport™ PCI-X Signal Name Ball B_AD5 AG7 B_AD6 AH7 B_AD7 AJ7 B_AD8 AF7 B_AD9 AE7 B_AD10 AG8 B_AD11 AE8 B_AD12 ...
Page 186
... AMD-8132™ HyperTransport™ PCI-X Table 34. Signals Sorted by Name B_C - L0_CADIN Signal Name Ball B_CAL AF8 B_CBE_L0 AH5 B_CBE_L1 AE9 B_CBE_L2 AE11 B_CBE_L3 AG10 B_CBE_L4__AD49 AE4 B_CBE_L5__AD48 AC6 B_CBE_L6 AE3 B_CBE_L7 AB6 B_DEVSEL_L AD7 B_ECC2 AE13 B_ECC3 AD13 B_ECC4 AC12 B_ECC5 ...
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... L0_CADOUT_H15 F4 L0_CADOUT_L0 N3 L0_CADOUT_L1 M2 L0_CADOUT_L2 L3 L0_CADOUT_L3 K2 L0_CADOUT_L4 H2 L0_CADOUT_L5 G3 L0_CADOUT_L6 F2 L0_CADOUT_L7 E3 L0_CADOUT_L8 P5 L0_CADOUT_L9 N6 L0_CADOUT_L10 M5 L0_CADOUT_L11 L6 L0_CADOUT_L12 J6 L0_CADOUT_L13 H5 Chapter 8 AMD-8132™ HyperTransport™ PCI-X Signal Name Ball L0_CADOUT_L14 G6 L0_CADOUT_L15 F5 L0_CLKIN_H0 C9 L0_CLKIN_H1 E10 L0_CLKIN_L0 B9 L0_CLKIN_L1 D10 L0_CLKOUT_H0 J2 L0_CLKOUT_H1 K4 L0_CLKOUT_L0 J3 L0_CLKOUT_L1 K5 L0_COMP_PD B2 L0_COMP_PU C3 L0_CTLIN_H0 B4 L0_CTLIN_L0 A4 L0_CTLOUT_H0 ...
Page 188
... AMD-8132™ HyperTransport™ PCI-X Table 36. Signals Sorted by Name L1_CADOUT - V33 Signal Name Ball L1_CADOUT_H0 B17 L1_CADOUT_H1 A18 L1_CADOUT_H2 B19 L1_CADOUT_H3 A20 L1_CADOUT_H4 A22 L1_CADOUT_H5 B23 L1_CADOUT_H6 A24 L1_CADOUT_H7 B25 L1_CADOUT_H8 D16 L1_CADOUT_H9 E17 L1_CADOUT_H10 D18 L1_CADOUT_H11 E19 L1_CADOUT_H12 E21 L1_CADOUT_H13 ...
Page 189
... VDD F12 VDD F14 VDD F16 VDD F18 VDD F20 VDD F22 VDD F24 VDD F27 VDD G15 Chapter 8 AMD-8132™ HyperTransport™ PCI-X Signal Name Ball VDD G9 VDD G11 VDD G13 VDD G17 VDD G19 VDD G21 VDD G23 VDD H3 ...
Page 190
... AMD-8132™ HyperTransport™ PCI-X Table 38. Signals Sorted by Name VDD - VIOA Signal Name Ball VDD M27 VDD N7 VDD N9 VDD N11 VDD N13 VDD N15 VDD N17 VDD N19 VDD N21 VDD N23 VDD P6 VDD P8 VDD P10 VDD P12 VDD P14 VDD ...
Page 191
... V14 VIOB W9 VIOB W11 VIOB W13 VIOB Y8 VIOB Y10 VIOB Y12 VIOB Y14 VLDT A14 VLDT B14 Chapter 8 AMD-8132™ HyperTransport™ PCI-X Signal Name Ball VLDT C14 VLDT P1 VLDT P2 VLDT P3 VLDT A16 VLDT B16 VLDT C16 VLDT P27 VLDT P28 ...
Page 192
... AMD-8132™ HyperTransport™ PCI-X Table 40. Signals Sorted by Name VSS - VSS Signal Name Ball VSS AH12 VSS AH15 VSS AH18 VSS AH21 VSS AH24 VSS AH27 VSS AJ15 VSS B27 VSS C1 VSS C2 VSS C15 VSS C28 VSS C29 VSS D7 VSS D9 VSS ...
Page 193
... R2 VSS R3 VSS R4 VSS R5 VSS R6 VSS R7 VSS R8 VSS R10 VSS R12 VSS R14 VSS R16 Chapter 8 AMD-8132™ HyperTransport™ PCI-X Signal Name Ball VSS R18 VSS R20 VSS R22 VSS R24 VSS R25 VSS R26 VSS R27 VSS T7 VSS T9 VSS T11 ...
Page 194
... AMD-8132™ HyperTransport™ PCI-X 8.1 Package Specification Figure 25. Package Mechanical Drawing. 194 ® 2.0 Tunnel Data Sheet Package and Pin Designations 26792 Rev. 3.07 July 2005 Chapter 8 ...
Page 195
... Rev. 3.07 July 2005 Appendix A Ordering Part Number AMD-8132 BL Appendix A AMD-8132™ HyperTransport™ PCI Delivery Packaging T = Tape and reel (These orders must W = Waffle pack (tray) (These orders RoHS Compliance F = RoHS compliant part Case Temperature C = Commercial temperature range Package Type ...
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... AMD-8132™ HyperTransport™ PCI-X 196 ® 2.0 Tunnel Data Sheet Ordering Part Number 26792 Rev. 3.07 July 2005 Appendix A ...