EW80314GS Q 099 Intel, EW80314GS Q 099 Datasheet - Page 32

• Manufacturer Part Number: EW80314GS Q 099
• Manufacturer: Intel

Specifications of EW80314GS Q 099

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Specification Clarifications
Specification Clarifications
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Byte swapping must be on data word-aligned boundaries
Performing byte swapping on data word-unaligned DMA transfers does not result in the correct
swapping. Data integrity is lost when the byte-swapping capability of the DMA engines is used on
data word-unaligned addresses. When the application in question requires byte swapping, consider
having the initial DMA transfer the data with an offset so that the data that needs swapping ends up
on a word-aligned address.
MISC_CSR register SOFT_RESET not only asserts the Px_RST pin but also
resets the PCI block
The SOFT_RESET bit in the MISC_CSR register (offset 0x040) not only asserts the Px_RST pin
on the bus, but also resets the corresponding PCI block. PCI soft-resets are not possible without
resetting the full corresponding PCI blocks.
SD_BANK_CTRL register programming restrictions
ACT to PRECHARGE timing problem when a refresh occurs. With regard to the
SD_BANK_CTRL register at offset 0x008, the sum of T_WR + T_RCD + 2 must be equal or
greater than T_RAS.
Multi-bit ECC error behaviors
When a multi-bit ECC error occurs in the second data phase of a burst write from the Intel XScale
processor into the 80314, the 80314 incorrectly forward the write to the destination. The correct
function is to disable the byte enables when forwarding a write transaction where the ECC was
detected. An interrupt is asserted upon detection of the ECC error. Target addresses meant to be
overwritten with good data are overwritten with corrupt data. Firmware must be aware that upon an
ECC error from an Intel XScale
Requirements for booting to other than an 8-bit PBI width
The 80314 PBI width is 8 bits by default. In order to boot from devices wider than 8 bits, a PROM
must be used on the I
include the use of an I
must be used.
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80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip Developer’s Manual
Intel
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C bus to reconfigure the PBI width appropriately. When a design does not
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C EEPROM for some initial device configuration, an 8-bit flash device
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80314 I/O Processor Companion Chip Specification Update
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processor write, the data is still written to the target
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