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AMD Geode™ LX Processors Data Book April 2006 Publication ID: 33234C AMD Geode™ LX Processors Data Book ...
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Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the ...
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Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Integrated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1-1. Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 6-42. Ancillary Data Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 2-1. Graphics Processor Feature Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 6-11. Data Only Command Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 6-66. Panel Output Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 8-15. mod base Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Overview 1.1 General Description The AMD Geode™ LX processors are integrated x86 pro- cessors specifically designed to power embedded devices for entertainment, education, and business. Serving the needs of consumers and business professionals alike, it’s an exellent solution for embedded ...
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Features General Features ■ Functional blocks include: — CPU Core — GeodeLink™ Control Processor — GeodeLink Interface Units — GeodeLink Memory Controller — Graphics Processor — Display Controller — Video Processor – TFT Controller/Video Output Port — Video ...
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Overview Display Controller ■ Hardware frame buffer compression improves Unified Memory Architecture (UMA) memory efficiency ■ CRT resolutions supported: — Supports up to 1920x1440x32 bpp — Supports up to 1600x1200x32 bpp at 100 Hz ■ Supports up ...
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Overview AMD Geode™ LX Processors Data Book ...
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Architecture Overview The CPU Core provides maximum compatibility with the vast amount of Internet content available while the intelli- gent integration of several other functions, including graph- ics, makes the AMD Geode™ LX processor a true system- level multimedia solution. ...
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Memory Management Unit The memory management unit (MMU) translates the linear address supplied by the integer unit into a physical address to be used by the cache unit and the internal bus interface unit. Memory management procedures are ...
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Architecture Overview 2.5 Graphics Processor The Graphics Processor is based on the graphics proces- sor used in the Geode GX processor with several new fea- tures to enhance performance and functionality. Like its predecessor, the Geode LX processor’s Graphics Proces- ...
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Display Controller The Display Controller performs the following functions: 1) Retrieves graphics, video, and cursor data. 2) Serializes the streams. 3) Performs any necessary color lookups and output for- matting. 4) Interfaces to the Video Processor for driving ...
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Architecture Overview 2.10 Security Block The Geode LX processor has an on-chip AES 128-bit crypto acceleration block capable of 44 Mbps throughput on either encryption or decryption at a processor speed of 500 MHz. The AES block runs asynchronously to ...
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Architecture Overview AMD Geode™ LX Processors Data Book ...
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Signal Definitions This chapter defines the signals and describes the external interface of the AMD Geode™ LX processor. Figure 3-1 shows the pins organized by their functional groupings. Where signals are multiplexed, the default signal name is listed first and ...
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Table 3-1. Video Signal Definitions Per Mode Signal Name CRT w/16-bit VIP RED RED GREEN GREEN BLUE BLUE DRGB[31:24] (I/O) VID[15:8] (I) DRGB[23:16] (O) R[7:0] DRGB[15:8] (O) G[7:0] DRGB[7:0] (O) B[7:0] DOTCLK (O) DOTCLK (O) HSYNC (O) HSYNC (O) ...
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Signal Definitions 3.1 Buffer Types The Ball Assignment tables starting on page 26 include a column labeled “Buffer Type”. The details of each buffer type listed in this column are given in Table 3-2. The col- umn headings in Table ...
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Bootstrap Options The bootstrap options shown in Table 3-3 are supported in the Geode LX processor for configuring the system. Table 3-3. Bootstrap Options Pins Description IRQ13 0: Normal boot operation, TAP reset active during PCI reset 1: ...
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Signal Definitions DQ21 V DQM2 ...
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Table 3-5. Ball Assignments - Sorted by Ball Number Ball Signal Name Type Buffer No. (Note 1) (PD) Type A1 V GND --- PWR --- MEM A3 V GND --- SS A4 DQ21 I/O DDR A5 ...
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Signal Definitions Table 3-5. Ball Assignments - Sorted by Ball Number (Continued) Ball Signal Name Type Buffer No. (Note 1) (PD) Type H2 V GND --- SS H3 DQS1 I/O DDR H4 SDCLK1N O DDRCLK H28 SDCLK3N O DDRCLK H29 ...
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Table 3-5. Ball Assignments - Sorted by Ball Number (Continued) Ball Signal Name Type Buffer No. (Note 1) (PD) Type Y2 DAV AGND --- PWR --- GND --- SS Y28 V PWR --- ...
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Signal Definitions Table 3-5. Ball Assignments - Sorted by Ball Number (Continued) Ball Signal Name Type Buffer No. (Note 1) (PD) Type AK4 DRGB14 O (PD) 24/Q5 VOP9 O AK5 V GND --- SS AK6 DRGB1 O (PD) 24/Q5 VOP6 ...
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Table 3-6. Ball Assignments - Sorted Alphabetically by Signal Name Signal Name Ball No. AD0 AJ19 AD1 AH19 AD2 AL20 AD3 AK20 AD4 AK19 AD5 AH21 AD6 AJ21 AD7 AL19 AD8 AK22 AD9 AL22 AD10 AK23 AD11 AH22 AD12 ...
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Signal Definitions Table 3-6. Ball Assignments - Sorted Alphabetically by Signal Name (Continued) Signal Name Ball No. DRGB7 AJ8 DRGB8 AJ2 DRGB9 AK3 DRGB10 AL3 DRGB11 AH5 DRGB12 AJ4 DRGB13 AL4 DRGB14 AK4 DRGB15 AJ5 DRGB16 AF2 DRGB17 AF1 DRGB18 ...
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Table 3-6. Ball Assignments - Sorted Alphabetically by Signal Name (Continued) Signal Name Ball No. VOP13 AL3 VOP14 AK3 VOP15 AJ2 VOP_BLANK AE4 VOPCLK AE1 VOP_HSYNC AE3 VOP_VSYNC AD3 V (Total A2, A14, B1, B5, B8, MEM of 33) ...
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Signal Definitions 3.4 Signal Descriptions 3.4.1 System Interface Signals Ball Signal Name No. Type SYSREF Y31 I DOTREF AB1 I INTA# AD28 I/O (PD) IRQ13 AB29 I/O (Strap) (PD) CIS AE29 I/O SUSPA# AC31 I/O (Strap) PW0, PW1 AL18, I/O ...
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System Interface Signals (Continued) Ball Signal Name No. Type TDN AK17 A 3.4.2 PLL Interface Signals Ball Signal Name No. Type CAV W31 APWR DD CAV W30 APWR SS MAV V31 APWR DD MAV V30 APWR SS VAV ...
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Signal Definitions 3.4.3 Memory Interface Signals (DDR) (Continued) Ball Signal Name No. Type CS[3:0]# D30, I/O F29, F28, B28 RAS[1:0]# D27, I/O C26 CAS[1:0]# E29, I/O E28 WE[1:0]# A28, I/O C27 BA[1:0] C20, I/O D26 MA[13:0] See I/O Table 3- ...
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Memory Interface Signals (DDR) (Continued) Ball Signal Name No. Type DQ[63:0] See I/O Table page 30 3.4.4 Internal Test and Measurement Interface Signals Ball Signal Name No. Type TCLK AC2 I TMS AA4 I TDI ...
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Signal Definitions 3.4.5 PCI Interface Signals Ball Signal Name No. Type AD[31:0] See I/O Table page 30 CBE[3:0]# AH31, I/O AH27, AL26, AJ22 PAR AJ27 I/O AMD Geode™ LX Processors Data Book f V Description 33-66 Mb/s ...
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PCI Interface Signals (Continued) Ball Signal Name No. Type RESET# Y30 I STOP# AJ25 I/O FRAME# AL28 I/O IRDY# AH25 I/O TRDY# AK26 I Description 0-1 Mb/s 3.3 PCI Reset. RESET# aborts all operations in ...
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Signal Definitions 3.4.5 PCI Interface Signals (Continued) Ball Signal Name No. Type DEVSEL# AK25 I/O REQ[2:0]# AB28, I AB31, AA29 GNT[2:0]# AC30, I/O AB30, AA28 (Strap) AMD Geode™ LX Processors Data Book f V Description 33-66 Mb/s 3.3 Device Select. ...
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TFT Display Interface Signals Ball Signal Name No. Type DRGB[31:24] See I/O Table 3- DRGB[23: (PD) page 30 DOTCLK AE1 O (PD) HSYNC AE3 O (PD) VSYNC AD3 O (PD) DISPEN AE4 O (PD) VDDEN ...
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Signal Definitions 3.4.7 CRT Display Interface Signals Ball Signal Name No. Type HSYNC AE3 I/O VSYNC AD3 I/O DVREF W1 A DRSET Y1 A DAV [3:0] W4, V4, APWR DD V1, U1 DAV [3:0] W2, Y2, AGND SS V3, U3 ...
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Power and Ground Interface Signals Signal Name Ball (Note 1) No. Type V See PWR CORE Table page 30 V See PWR IO Table page 30 V See PWR MEM Table 3- ...
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Signal Definitions Table 3-7. Signal Behavior During and After Reset Signal Name Type Behavior AD[31:0] PCI TRI-STATE during RESET# low INTA# PAR REQ# IRDY# FRAME# GNT# DEVSEL# TRDY# STOP# BA[1:0] DDR CAS[1:0]# CBE[3:0]# CS[3:0]# DQ[63:0] DQM[7:0] DQS[7:0] MA[13:0] RAS[1:0]# SDCLK[5:0]P ...
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Signal Definitions AMD Geode™ LX Processors Data Book ...
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GeodeLink™ Interface Unit Many traditional architectures use buses to connect mod- ules together, which usually requires unique addressing for each register in every module. This requires that some kind of house-keeping be done as new modules are designed and new ...
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Port Address Each GLIU has seven channels with Channel 0 being the GLIU itself and therefore not considered a physical port. Figure 4-1 illustrates the GeodeLink architecture in a Geode LX processor, showing how the modules are con- ...
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GeodeLink™ Interface Unit 4.1.2 Port Addressing Exceptions There are some exceptions to the port addressing rules module accesses an MSR from within its closest GLIU (e.g., CPU Core accessing a GLIU0 MSR), then, by con- vention, the port ...
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Each memory request is compared against all the P2D descriptors. If the memory request does not hit in any of the descriptors, the request is sent to the subtractive port. If the memory requests hit more than one descriptor, ...
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GeodeLink™ Interface Unit 4.1.3.2 I/O Routing and Translation I/O addresses are routed and are never translated. I/O request routing is performed with a choice of two descriptor types. Each GLIU may have any number of each descriptor type. The IOD ...
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GLIU Register Descriptions All GeodeLink™ Interface Unit (GLIU) registers are Model Specific Registers (MSRs) and are accessed through the RDMSR and WRMSR instructions. The registers associated with the GLIU are the Standard GeodeLink Device (GLD) MSRs, GLIU Specific ...
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GLIU Register Descriptions Table 4-6. GLIU Specific MSRs Summary (Continued) MSR Address Type Register Name GLIU0: 10000089h RO SLAVE_ONLY GLIU1: 40000089h GLIU0: 1000008Ah RO Reserved GLIU1: 4000008Ah GLIU0: 1000008Bh RO WHO AM I (WHOAMI) GLIU1: 4000008Bh GLIU0: 1000008Ch R/W GLIU ...
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Table 4-7. GLIU Statistic and Comparator MSRs Summary (Continued) MSR Address Type Register GLIU0: 100000C0h R/W Request Compare Value GLIU1: 400000C0h (RQ_COMPARE_VAL[0]) GLIU0: 100000C1h R/W Request Compare Mask GLIU1: 400000C1h (RQ_COMPARE_MASK[0]) GLIU0: 100000C2h R/W Request Compare Value GLIU1: 400000C2h ...
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GLIU Register Descriptions Table 4-7. GLIU Statistic and Comparator MSRs Summary (Continued) MSR Address Type Register GLIU0: 100000DEh R/W Data Compare Mask Low GLIU1: 400000DEh (DA_COMPARE_MASK_LO[3]) GLIU0: 100000DFh R/W Data Compare Mask High GLIU1: 400000DFh (DA_COMPARE_MASK_HI[3]) Table 4-8. GLIU P2D ...
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Table 4-10. GLIU IOD Descriptor MSRs Summary MSR Address Type Register GLIU0 100000E0h- R/W IOD Base Mask Descriptors (IOD_BM) 100000E2h 100000E3h- R/W IOD Swiss Cheese Descriptors (IOD_SC) 100000E8h 100000E9h- R/W IOD Reserved Descriptors 100000FFh GLIU1 400000E0h- R/W IOD Base ...
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GLIU Register Descriptions 4.2.1 Standard GeodeLink™ Device (GLD) MSRs 4.2.1.1 GLD Capabilities MSR (GLD_MSR_CAP) MSR Address GLIU0: 10002000h GLIU1: 40002000h Type RO Reset Value 00000000_000014xxh ...
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GLD SMI MSR (GLD_MSR_SMI) MSR Address GLIU0: 10002002h GLIU1: 40002002h Type R/W Reset Value 00000000_00000001h The flags are set with internal conditions. The internal conditions are always capable of setting the flag, but if the mask is 1, ...
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GLIU Register Descriptions 4.2.1.4 GLD Error MSR (GLD_MSR_ERROR) MSR Address GLIU0: 10002003h GLIU1: 40002003h Type R/W Reset Value 00000000_00000000h The flags are set with internal conditions. The internal conditions are always capable of setting the flag, but if the mask ...
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GLD Bit Name Description 39 EFLAG7 Request Comparator Error Flag 0. If high, records that an ERR was generated due to a Request Comparator 0 (RQ_COMPARE_VAL0, GLIU0 MSR 100000C0h, GLIU1 MSR 400000C0h) event. Write 1 to clear; writing 0 ...
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GLIU Register Descriptions GLD Bit Name Description 8 EMASK8 Request Comparator Error Mask 1. Write 0 to enable EFLAG8 (bit 40) and to allow a Request Comparator 1 (RQ_COMPARE_VAL1, GLIU0 MSR 100000C2h, GLIU1 MSR 400000C2h) event to generate an ERR ...
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Bit Name Description 63:4 RSVD Reserved. 3:2 PMODE_1 Power Mode 1. Statistics and Time Slice Counters. 00: Disable clock gating. Clocks are always on. 01: Enable hardware clock gating. Clock goes off whenever this module’s circuits are not busy. ...
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GLIU Register Descriptions 4.2.2.2 Port Active Enable (PAE) MSR Address GLIU0: 10000081h GLIU1: 40000081h Type R/W Reset Value Boot Strap Dependent Ports that are not implemented return 00 (RSVD). Ports that are slave only return 11. Master/Slave ports return the ...
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Arbitration (ARB) MSR Address GLIU0: 10000082h GLIU1: 40000082h Type R/W Reset Value 10000000_00000000h ...
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GLIU Register Descriptions Bit Name Description 63:16 RSVD Reserved. 15 ASMI_MASK7 Asynchronous SMI Mask For Port 7 (GLIU0: Not Used; GLIU1: Not Used). Write 0 to allow Port 7 to generate an ASMI. ASMI status is reported in bit 7. ...
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33234C ...
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GLIU Register Descriptions 4.2.2.6 GLIU Physical Capabilities (PHY_CAP) MSR Address GLIU0: 10000086h GLIU1: 40000086h Type R/W Reset Value GLIU0: 20291830_010C1086h GLIU1: 20311030_0100400Ah ...
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N Outstanding Response (NOUT_RESP) MSR Address GLIU0: 10000087h GLIU1: 40000087h Type RO Reset Value 00000000_00000000h ...
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GLIU Register Descriptions 4.2.2.8 N Outstanding Write Data (NOUT_WDATA) MSR Address GLIU0: 10000088h GLIU1: 40000088h Type RO Reset Value 00000000_00000000h ...
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WHO AM I (WHOAMI) MSR Address GLIU0: 1000008Bh GLIU1: 4000008Bh Type RO Reset Value Configuration Dependent ...
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GLIU Register Descriptions Bit Name Description 63:8 RSVD Reserved. 7 SLAVE_DIS7 Slave Transactions Disable for Port 7 (GLIU0: Not Used; GLIU1: Not Used). Write 1 to disable slave transactions to Port 7. 6 SLAVE_DIS6 Slave Transactions Disable for Port 6 ...
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GLIU Statistic and Comparator MSRs 4.2.3.1 Descriptor Statistic Counter (STATISTIC_CNT[0:3]) Descriptor Statistic Counter (STATISTIC_CNT[0]) MSR Address GLIU0: 100000A0h GLIU1: 400000A0h Type R/W Reset Value 00000000_00000000h Descriptor Statistic Counter (STATISTIC_CNT[1]) MSR Address GLIU0: 100000A4h GLIU1: 400000A4h Type R/W Reset ...
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GLIU Register Descriptions 4.2.3.2 Statistic Mask (STATISTIC_MASK[0:3] Descriptor Statistic Mask (STATISTIC_MASK[0]) MSR Address GLIU0: 100000A1h GLIU1: 400000A1h Type R/W Reset Value 00000000_00000000h Descriptor Statistic Mask (STATISTIC_MASK[1]) MSR Address GLIU0: 100000A5h GLIU1: 400000A5h Type R/W Reset Value 00000000_00000000h ...
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Statistic Action (STATISTIC_ACTION[0:3] Descriptor Statistic Action (STATISTIC_ACTION[0]) MSR Address GLIU0: 100000A2h GLIU1: 400000A2h Type R/W Reset Value 00000000_00000000h Descriptor Statistic Action (STATISTIC_ACTION[1]) MSR Address GLIU0: 100000A6h GLIU1: 400000A6h Type R/W Reset Value 00000000_00000000h ...
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GLIU Register Descriptions STATISTIC_ACTION[0:3] Bit Descriptions Bit Name Description 2 HIT_ASMI Assert ASMI on Descriptor Hit. The descriptor hits are ANDed with the masks and then all ORed together. 0: Disable. 1: Enable. 1 HIT_DEC Decrement Counter on Descriptor Hit. ...
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Request Compare Mask (RQ_COMPARE_MASK[0:3] The RQ Compare Value and the RQ Compare Mask enable traps on specific transactions. A hit to the RQ Compare is determined by hit = (RQ_IN & RQ_COMPARE_MASK) == RQ_COMPARE_VAL). A hit can trigger ...
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GLIU Register Descriptions 4.2.3.6 DA Compare Value Low (DA_COMPARE_VAL_LO[0:3] The DA Compare Value and the DA Compare Mask enable traps on specific transactions. A hit to the DA Compare is deter- mined by hit = (DA_IN & DA_COMPARE_MASK) == DA_COMPARE_VAL). ...
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DA Compare Value High (DA_COMPARE_VAL_HI[0:3] The DA Compare Value and the DA Compare Mask enable traps on specific transactions. A hit to the DA Compare is deter- mined by hit = (DA_IN & DA_COMPARE_MASK) == DA_COMPARE_VAL). A hit ...
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GLIU Register Descriptions 4.2.3.8 DA Compare Mask Low (DA_COMPARE_MASK_LO[0:3]) Data Compare Mask Low (DA_COMPARE_MASK_LO[0]) MSR Address GLIU0: 100000D2h GLIU1: 400000D2h Type R/W Reset Value 00000000_00000000h Data Compare Mask Low (DA_COMPARE_MASK_LO[1]) MSR Address GLIU0: 100000D6h GLIU1: 400000D6h Type R/W Reset Value ...
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DA_COMPARE_MASK_HI[0:3]) 4.2.3.9 DA Compare Mask High ( Data Compare Mask High (DA_COMPARE_MASK_HI[0]) MSR Address GLIU0: 100000D3h GLIU1: 400000D3h Type R/W Reset Value 00000000_00000000h Data Compare Mask High (DA_COMPARE_MASK_HI[1]) MSR Address GLIU0: 100000D7h GLIU1: 400000D7h Type R/W Reset Value 00000000_00000000h ...
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GLIU Register Descriptions 4.2.4 P2D Descriptor Registers P2D descriptors are ordered P2D_BM, P2D_BMO, P2D_R, P2D_RO, P2D_SC, P2D_BMK. For example if NP2D_BM=3 and NP2D_BM0=2, IMSR EO = P2D_BM[0], MSR E3 = P2D_SC[0]. 4.2.4.1 P2D Base Mask Descriptor (P2D_BM) GLIU0 P2D_BM[5:0] MSR ...
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P2D Base Mask Offset Descriptor (P2D_BMO) GLIU0 P2D_BMO[1:0] MSR Address 10000026h-10000027h Type R/W Reset Value 00000FF0_FFF00000h See Table 4.1.3.1 "Memory Routing and Translation" on page 47 for details on the descriptor usage ...
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GLIU Register Descriptions 4.2.4.3 P2D Range Descriptor (P2D_R) GLIU0 P2D_R[0] MSR Address 10000028h Type R/W Reset Value 00000000_000FFFFFh See Table 4.1.3.1 "Memory Routing and Translation" on page 47 for details on the descriptor usage ...
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P2D Range Offset Descriptor (P2D_RO) GLIU0 P2D_RO[3:0] MSR Address 10000029h-1000002Bh Type R/W Reset Value 00000000_000FFFFFh See Table 4.1.3.1 "Memory Routing and Translation" on page 47 for details on the descriptor usage ...
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GLIU Register Descriptions 4.2.4.5 P2D Swiss Cheese Descriptor (P2D_SC) GLIU0 P2D_SC[0] MSR Address 1000002Ch Type R/W Reset Value 00000000_00000000h See Table 4.1.3.1 "Memory Routing and Translation" on page 47 for details on the descriptor usage ...
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SPARE MSRs (SPARE_MSR[0:9], A:F) MSR Address GLIU0: 10000040h-1000004Fh GLIU1: 40000040h-4000004Fh Type R/W Reset Value 00000000_00000000h ...
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GLIU Register Descriptions 4.2.6 I/O Descriptors I/O descriptors are ordered IOD_BM, IOD_SC. For example if NIOD_BM = 3 and NIOD_SC = 2, MSR 100000EOh = IOD_BM[0] and MSR 100000E3h = IOD_SC[0]. 4.2.6.1 IOD Base Mask Descriptors (IOD_BM) GLIU0 IOD_BM[0:3] MSR ...
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IOD Swiss Cheese Descriptors (IOD_SC) GLIU0 IOD_SC[0:5] MSR Address 100000E3h-100000E8h Type R/W Reset Value 00000000_00000000h See Table 4.1.3.1 "Memory Routing and Translation" on page 47 for details on the descriptor usage ...
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CPU Core This section describes the internal operations of the AMD Geode™ LX processor’s CPU Core from a programmer’s point of view. It includes a description of the traditional “core” processing and FPU operations. The integrated function registers are described ...
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Instruction Set Overview The CPU Core instruction set can be divided into nine types of operations: • Arithmetic • Bit Manipulation • Shift/Rotate • String Manipulation • Control Transfer • Data Transfer • Floating Point • High-Level Language ...
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CPU Core 5.3 Application Register Set The Application Register Set consists of the registers most often used by the applications programmer. These regis- ters are generally accessible, although some bits in the EFLAGS registers are protected. The General Purpose register ...
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General Purpose Registers The General Purpose registers are divided into four data registers, two pointer registers, and two index registers as shown in Table 5-2 on page 89. The Data registers are used by the applications program- mer ...
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CPU Core 5.3.4 EFLAGS Register The EFLAGS register contains status information and con- trols certain operations on the Geode LX processor. The Bit Name Flag Type Description 31:22 RSVD -- Reserved. Set System Identification Bit. The ...
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System Register Set The System Register Set, shown in Table 5-5, consists of registers not generally used by application programmers. These registers are either initialized by the system BIOS or employed by system level programmers who generate operating ...
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CPU Core 5.4.1 Control Registers A map of the Control registers (CR0, CR1, CR2, CR3, and CR4) is shown in Table 5-6 and the bit descriptions are in the tables that follow. (These registers should not be con- fused with ...
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Bit Name Description 31:9 RSVD Reserved. Set to 0 (always returns 0 when read). 8 PCE Performance Counter Enable. Set PCE = 1 to make RDPMC available at nonzero privi- lege levels. 7 PGE Page Global Enable. Set PGE ...
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CPU Core Table 5-10. CR0 Bit Descriptions (Continued) Bit Name Description 30 CD Cache Disable/Not Write-Through (Snoop). Cache behavior is based on the CR0 CD and NW bits 28:19 RSVD Reserved ...
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Table 5-11. Effects of Various Combinations of EM, TS, and MP Bits CR0[3: Instruction Type MP WAIT 0 Execute 1 ...
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CPU Core Register Descriptions 5.5 CPU Core Register Descriptions All CPU Core registers are Model Specific Registers (MSRs) and are accessed via the RDMSR and WRMSR instructions. Each module inside the processor is assigned a 256 regis- ter section of ...
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Table 5-13. CPU Core Specific MSRs Summary (Continued) MSR Address Type Register Name 00001110h RO IF Sequential Count MRS (IF_SEQCOUNT_MSR) 00001140h RO IF Built-In Self-Test MSR (IF_BIST_MSR) 00001210h R/W Exception Unit (XC) Configuration MSR (XC_CONFIG_MSR) 00001211h R/W XC Mode ...
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CPU Core Register Descriptions Table 5-13. CPU Core Specific MSRs Summary (Continued) MSR Address Type Register Name 00001335h R/W GS Segment Base/Limit MSR (GS_BASE_MSR) 00001336h R/W LDT Segment Base/Limit MSR (LDT_BASE_MSR) 00001337h R/W Temp Segment Base/Limit MSR (TEMP_BASE_MSR) 00001338h R/W ...
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Table 5-13. CPU Core Specific MSRs Summary (Continued) MSR Address Type Register Name 00001374h R/W Floating Point Environment Opcode Pointer (FPENV_OP_MSR) 00001380h RO Address Calculation Unit Configuration MSR (AC_CONFIG_MSR) 00001408h R/W General Register EAX MSR (GR_EAX_MSR) 00001409h R/W General ...
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CPU Core Register Descriptions Table 5-13. CPU Core Specific MSRs Summary (Continued) MSR Address Type Register Name 00001722h R/W ITB Entry MSR (ITB_ENTRY_MSR) 00001723h R/W ITB Entry with Increment MSR (ITB_ENTRY_I_MSR) 00001724h R/W ITB L0 Cache Entry MSR (ITB_L0_ENTRY_MSR) 00001730h ...
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Table 5-13. CPU Core Specific MSRs Summary (Continued) MSR Address Type Register Name 00001813h R/W Region Configuration Range 3 MSR (RCONF3_MSR) 00001814h R/W Region Configuration Range 4 MSR (RCONF4_MSR) 00001815h R/W Region Configuration Range 5 MSR (RCONF5_MSR) 00001816h R/W ...
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CPU Core Register Descriptions Table 5-13. CPU Core Specific MSRs Summary (Continued) MSR Address Type Register Name 00001901h R/W Bus Controller Configuration 1 MSR (BC_CONFIG1_MSR) 00001904h RO Reserved Status MSR (RSVD_STS_MSR) 00001908h R/W MSR Lock MSR (MSR_LOCK_MSR) 00001910h R/W Real ...
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Table 5-13. CPU Core Specific MSRs Summary (Continued) MSR Address Type Register Name 00001A03h R/W FPU Reserved MSR (FPU_RSVD_MSR) 00001A10h R/W FPU x87 Control Word MSR (FPU_CW_MSR) 00001A11h R/W FPU x87 Status Word MSR (FPU_SW_MSR) 00001A12h R/W FPU x87 ...
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CPU Core Register Descriptions Table 5-13. CPU Core Specific MSRs Summary (Continued) MSR Address Type Register Name 00003000h R/W Standard Levels and Vendor ID String 1 (CPUID0_MSR) 00003001h R/W Vendor ID Strings 2 and 3 (CPUID1_MSR) 00003002h R/W Type/Family/Model/Step (CPUID2_MSR) ...
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Standard GeodeLink™ Device MSRs 5.5.1.1 GLD Capabilities MSR (GLD_MSR_CAP) MSR Address 00002000h Type RO Reset Value 00000000_000860xxh ...
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CPU Core Register Descriptions 5.5.1.3 GLD SMI MSR (GLD_MSR_SMI) MSR Address 00002002h Type R/W Reset Value 00000000_00000000h This register is not used in the CPU Core module. 5.5.1.4 GLD Error MSR (GLD_MSR_ERROR) MSR Address 00002003h Type R/W Reset Value 00000000_00000000h ...
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CPU Core Specific MSRs 5.5.2.1 Time Stamp Counter MSR (TSC_MSR) MSR Address 00000010h Type R/W Reset Value 00000000_00000000h ...
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CPU Core Register Descriptions 5.5.2.3 Performance Event Counter 1 MSR (PERF_CNT1_MSR) MSR Address 000000C2h Type R/W Reset Value 00000000_00000000h ...
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SYS_CS_MSR Bit Descriptions (Continued) Bit Name Description 17 R (RO) Readable (Read Only). Code segment is readable. (Default = (RO) Accessed (Read Only). Code segment was accessed. (Default = 1) 15:3 CS_SEL Code Segment Selector. (Default ...
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CPU Core Register Descriptions 5.5.2.7 Performance Event Counter 0 Select MSR (PERF_SEL0_MSR MSR Address 00000186h Type R/W Reset Value 00000000_00000000h ...
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Instruction Fetch Configuration MSR (IF_CONFIG_MSR) MSR Address 00001100h Type R/W Reset Value 00000000_00005051h IF_CONFG_MSR controls the operation of the Instruction Fetch (IF). The Level-0 COF cache (Change of Flow (COF) cache), L1 COF cache, return stack, and power ...
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CPU Core Register Descriptions IF_CONFIG_MSR Bit Descriptions (Continued) Bit Name Description 28 II_NS Instruction Pipeline (IP) Empty Mode Interface may make requests to Instruction Memory (IM) when the IP is not empty. (Default Interface only makes ...
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IF_CONFIG_MSR Bit Descriptions (Continued) Bit Name Description 6 STRONG Strong Prediction. Allow the IF to make strong predictions. 0: Disable. 1: Enable. (Default) Note: 5 RSVD Reserved Return Stack. 0: Disable. 1: Enable. (Default) Note: 3 RSVD ...
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CPU Core Register Descriptions Bit Name Description 63:2 RSVD Reserved Invalidate Return Stack not alter the return stack. (Default) 1: Empty the return stack Invalidate L0 and L1 COF Cache not alter ...
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IF_TEST_ADDR_MSR Bit Descriptions (Continued) Bit Name Description 12:8 BLOCK Block Identifier. 00h: Target RAM 0 (Way 0). (Default) 01h: Target RAM 1 (Way 0). 02h: Target RAM 2 (Way 0). 03h: Target RAM 3 (Way 0). 04h: Target RAM ...
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CPU Core Register Descriptions IF_TEST_DATA_MSR Register Map for Tag RAMs ...
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IF_TEST_DATA_MSR Register Map for Level-0 COF Cache Tag ...
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CPU Core Register Descriptions IF_TEST_DATA_MSR Register Map for Level-0 COF Cache Address ...
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IF_TEST_DATA_MSR Register Map for Return Stack Valids ...
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CPU Core Register Descriptions 5.5.2.14 IF Built-In Self-Test MSR (IF_BIST_MSR) MSR Address 00001140h Type RO Reset Value 00000000_00000000h IF_BIST_MSR may be used to run built-in self-test (BIST) on the IF Tag and Target RAMs, and to get an indication of ...
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Exception Unit (XC) Configuration MSR (XC_CONFIG_MSR) MSR Address 00001210h Type R/W Reset Value 00000000_00000000h XC_CONFIG_MSR allows the processor to be configured so that when the processor is in its HALT state, it can request that its clocks be ...
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CPU Core Register Descriptions Bit Name Description 63:16 RSVD (RO) Reserved (Read Only). 15 DM_AC_STALL Data Memory Subsystem Stall Address Calculation Unit (Read Only). DM wants no (RO) more requests from AC. 14 FP_STALL (RO) Floating Point Stall (Read Only). ...
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XC_HIST_MSR Bit Descriptions (Continued) Bit Name Description (Note 1) 46:42 TYPE8 Exception Type 8. 41:37 TYPE7 Exception Type 7. 36:32 TYPE6 Exception Type 6. 31:30 RSVD Reserved. 29:25 TYPE5 Exception Type 5. 24:20 TYPE4 Exception Type 4. 19:15 TYPE3 ...
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CPU Core Register Descriptions XC_UADDR_MSR Bit Descriptions (Continued) Bit Name Description 59:48 UADDR4 Microcode Address for Exception 4. 47:36 UADDR3 Microcode Address for Exception 3. 35:24 UADDR2 Microcode Address for Exception 2. 23:12 UADDR1 Microcode Address for Exception 1. 11:0 ...
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SMM Control MSR (SMM_CTL_MSR) MSR Address 00001301h Type R/W Reset Value 00000000_00000000h ...
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CPU Core Register Descriptions 5.5.2.21 Debug Management Interrupt (DMI) Control Register MSR Address 00001302h Type R/W Reset Value 00000000_00000000h ...
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DMI Control Register Bit Descriptions (Continued) Bit Name Description 1 DMI_GPF DMI General Protection Faults. When enabled and not in DMM mode, allow general protection faults to generate DMIs. 0: Disable. 1: Enable. 0 DMI_INST DMI Instructions. Enable DMI ...
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CPU Core Register Descriptions 5.5.2.23 Segment Selector/Flags MSRs The Segment Selector/Flags MSRs provide access to the segment selector and segment flags parts of a segment register. The contents of segment registers should be accessed using MOV or SVDC/RSDC. ES Segment ...
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Segment Selector/Flags MSR Bit Descriptions (Continued) Bit Name Description 19 X Executable Non-System Segment. 18 E/C Expand Down Data Segment / Conforming Code Segment. 17 W/R Writable Data Segment / Readable Code Segment Accessed Segment. 15:3 SELECTOR ...
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CPU Core Register Descriptions 5.5.2.25 DMM Header MSR (DMM_HDR_MSR) MSR Address 0000132Ch Type R/W Reset Value 00000000_00000000h DMM_HDR_MSR provides access to the address register that controls where DMI data is written ...
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Segment Base/Limit MSRs The segment base/limit MSRs provide access to the segment limit and segment base parts of a segment register. The limit value is the true limit; it does not need to be altered based on the ...
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CPU Core Register Descriptions 5.5.2.27 Debug Registers 1 and 0 MSR (DR1_DR0_MSR) MSR Address 00001340h Type R/W Reset Value xxxxxxxx_xxxxxxxxh DR1_DR0_MSR provides access to Debug Register 1 (DR1) and Debug Register 0 (DR0). DR0 and DR1 each contain either an ...
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Debug Registers 7 and 6 MSR (DR6_DR7_MSR) MSR Address 00001343h Type R/W Reset Value 00000000_FFFF0000h DR7_DR6_MSR provides access to Debug Register 7 (DR7) and Debug Register 6 (DR6). DR6 contains status informa- tion about debug conditions that have ...
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CPU Core Register Descriptions 5.5.2.30 Extended Debug Registers 1 and 0 MSR (XDR1_XDR0_MSR) MSR Address 00001350h Type R/W Reset Value 00000000_00000000h XDR1/XDR0_MSR provides access to Extended Debug Register 1 (XDR1) and Extended Debug Register 0 (XDR0). XDR0 and XDR1 each ...
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Extended Debug Registers 5 and 4 MSR (XDR5_XDR4_MSR) MSR Address 00001352h Type R/W Reset Value FFFFFFFF_00000000h XDR5/XDR4_MSR provides access to Extended Debug Register 5 (XDR5) and Extended Debug Register 4 (XDR4). XDR4 contains an opcode match value. XDR5 ...
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CPU Core Register Descriptions Bit Name Description 63:62 LEN3 Extended Breakpoint 3 Length. 61:60 TYPE3 Extended Breakpoint 3 Type. 59:58 LEN2 Extended Breakpoint 2 Length. 57:56 TYPE2 Extended Breakpoint 2 Type. 55:54 LEN1 Extended Breakpoint 1 Length. 53:52 TYPE1 Extended ...
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Extended Debug Registers 9 and 8 MSR (XDR9_XDR8_MSR) MSR Address 00001354h Type R/W Reset Value FFFFFFFF_00000000h XDR9_XDR8_MSR provides access to Extended Debug Register 9 (XDR9) and Extended Debug Register 8 (XDR8). XDR8 contains an opcode match value. XDR9 ...
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CPU Core Register Descriptions 5.5.2.35 Extended Debug Registers 11 and 10 MSR (XDR11_XDR10_MSR) MSR Address 00001355h Type R/W Reset Value xxxxxxxx_xxxx0000h XDR11_XDR10_MSR provides access to the extended I/O breakpoint ...
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WB Stage Instruction Pointer MSR (WB_IP_MSR) MSR Address 00001361h Type R/W Reset Value 00000000_00000000h WB_IP_MSR provides access to the WB stage instruction pointer (effective address ...
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CPU Core Register Descriptions 5.5.2.39 WB Stage Linear Instruction Pointer MSR (WB_LIP_MSR) MSR Address 00001365h Type RO Reset Value 00000000_00000000h WB_LIP_MSR provides access to the WB stage linear instruction pointer ...
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C3/C2 Linear Instruction Pointer MSR (C3_C2_LIP_MSR) MSR Address 00001367h Type RO Reset Value 00000000_00000000h C3_C2_LIP_MSR provides access to linear instruction pointers when the code segment was loaded ...
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CPU Core Register Descriptions 5.5.2.43 Floating Point Environment Instruction Pointer (FPENV_IP_MSR) MSR Address 00001371h Type R/W Reset Value 00000000_00000000h FPENV_IP_MSR provides access to the floating point (FP) environment instruction pointer. Software better accesses the floating point environment data using the ...
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Floating Point Environment Data Pointer (FPENV_DP_MSR) MSR Address 00001373h Type R/W Reset Value 00000000_00000000h FPENV_DP_MSR provides access to the floating point (FP) environment data pointer. Software better accesses the float- ing point environment data using the FLDENV/FSTENV and ...
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CPU Core Register Descriptions 5.5.2.47 Address Calculation Unit Configuration MSR (AC_CONFIG_MSR) MSR Address 00001380h Type RO Reset Value 00000000_00000000h ...
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General Register MSRs General Register EAX MSR (GR_EAX_MSR) MSR Address 00001408h Type R/W Reset Value 00000000_00000000h General Register ECX MSR (GR_ECX_MSR) MSR Address 00001409h Type R/W Reset Value 00000000_00000000h General Register EDX MSR (GR_EDX_MSR) MSR Address 0000140Ah Type ...
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CPU Core Register Descriptions 5.5.2.49 Extended Flags MSR (EFLAG_MSR) MSR Address 00001418h Type R/W Reset Value 00000000_00000002h ...
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Instruction Memory Configuration MSR (IM_CONFIG_MSR) MSR Address 00001700h Type R/W Reset Value 00000000_00000000h ...
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CPU Core Register Descriptions IM_CONFIG_MSR Bit Descriptions (Continued) Bits Name Description 8 ICD Instruction Cache Disable. Completely disable L0 and L1 instruction caches. Contents of cache is not modified and no cache entry is read. 0: Use standard x86 cacheability ...
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Instruction Cache Index MSR (IC_INDEX_MSR) MSR Address 00001710h Type R/W Reset Value 00000000_00000000h ...
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CPU Core Register Descriptions 5.5.2.54 Instruction Cache Tag (IC_TAG_MSR) MSR Address 00001712h Type R/W Reset Value 00000000_00000000h ...
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Instruction Cache Tag with Increment (IC_TAG_I_MSR) MSR Address 00001713h Type R/W Reset Value 00000000_00000000h ...
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CPU Core Register Descriptions Bits Name Description 63:32 RSVD Reserved. 31:16 TLB_NUM TLB Number. This is the one-hot-value of the TLB entry corresponding to the L0 cache entry. (Default = 0) 15:12 RSVD Reserved. 11:8 TAG Tag/Line. This is a ...
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L1 Instruction TLB Least Recently Used MSR (ITB_LRU_MSR) MSR Address 00001721h Type R/W Reset Value 00000000_00000000h ...
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CPU Core Register Descriptions 5.5.2.60 L1 Instruction TLB Entry MSRs ITB Entry MSR (ITB_ENTRY_MSR) MSR Address 00001722h Type R/W Reset Value xxxxxxxx_xxxxxxxxh ITB Entry with Increment MSR (ITB_ENTRY_I_MSR) MSR Address 00001723h Type R/W Reset Value xxxxxxxx_xxxxxxxxh ITB_ENTRY_MSR, ITB_ENTRY_I_MSR, ITB_L0_ENTRY_MSR Register ...
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Instruction Memory Subsystem BIST Tag MSR (IM_BIST_TAG_MSR) MSR Address 00001730h Type RO Reset Value 00000000_0000000xh The Instruction Memory subsystem supports built-in self-test (BIST) for the tag and data arrays. Normally, BIST is run dur- ing manufacturing test. For ...
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CPU Core Register Descriptions 5.5.2.63 Data Memory Subsystem Configuration 0 MSR (DM_CONFIG0_MSR) MSR Address 00001800h Type R/W Reset Value 00000000_00000000h ...
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DM_CONFIG0_MSR Bit Descriptions (Continued) Bits Name Description 32 WBDIS Write Buffer Disable. Disabling the write buffer forces stores to be sent directly from the output of the store queue to the bus controller. Enabling the write buffer allows memory ...
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CPU Core Register Descriptions DM_CONFIG0_MSR Bit Descriptions (Continued) Bits Name Description 7 SPCDEC Decrease Number of Speculative Reads of Data Cache. 0: Actively resync cache tag and data arrays so that loads can be speculatively handled in one clock if ...
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Data Memory Subsystem Configuration 1 MSR (DM_CONFIG1_MSR) MSR Address 00001801h Type R/W Reset Value 00000000_00000000h ...
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CPU Core Register Descriptions DM_CONFIG1_MSR Bit Descriptions (Continued) Bits Name Description 20 NOPFXEVCT No Prefetch Prefix Evictions. This bit disables clean line eviction in the case where a new allocation occurs on a load/store miss when a move string operation ...
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Bits Name Description 63:48 PFLOCKT2 Prefetch Lockout of PREFETCHT2. Bit mask of ways that cannot be allocated or replaced on a data prefetch miss on a PREFECTHT2 instruction. If all ways are locked, PREFETCHT2 is effectively disabled. Use this ...
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CPU Core Register Descriptions 5.5.2.67 Region Configuration Bypass MSR (RCONF_BYPASS_MSR) MSR Address 0000180Ah Type R/W Reset Value 00000000_00000101h Warm Start Value 00000000_00000219h ...
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Region Configuration C0000-DFFFF MSR (RCONF_C0_DF_MSR) MSR Address 0000180Ch Type R/W Reset Value 01010101_01010101h Warm Start Value 19191919_19191919h ...
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CPU Core Register Descriptions Bit Name Description 63:56 RPFC Region Properties for 000FC000-000FFFFF. 55:48 RPF8 Region Properties for 000F8000-000FBFFF. 47:40 RPF4 Region Properties for 000F4000-000FAFFF. 39:32 RPF0 Region Properties for 000F0000-000F3FFF. 31:24 RPEC Region Properties for 000EC000-000EFFFF. 23:16 RPE8 Region ...
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Region Configuration DMM MSR (RCONF_DMM_MSR) MSR Address 0000180Fh Type R/W Reset Value 00000001_00000001h Warm Start Value xxxxx001_xxxxx005h ...
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CPU Core Register Descriptions 5.5.2.73 Region Configuration Range MSRs 0 through 7 Region Configuration Range 0 MSR (RCONF0_MSR) MSR Address 00001810h Type R/W Reset Value 00000000_00000000h Warm Start Value xxxxx000_xxxxx0xxh Region Configuration Range 1 MSR (RCONF1_MSR) MSR Address 00001811h Type ...
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Region Properties The region properties consist of an 8-bit field as shown in Table 5-15. Table 5-16 and Table 5-17 describe the various region properties effects on read and write operations. Note that the cache is always interrogated even ...
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CPU Core Register Descriptions Table 5-17. Write Operations vs. Region Properties (Continued Note: “x” indicates setting ...
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Control Registers MSRs (CR1, CR2, CR3, CR4) These are the standard x86 Control Registers CR1, CR2, CR3, and CR4. CR0 is located at MSR 00001420h (see Section 5.5.2.50 on page 147). The contents of CR0-CR4 should only ...
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CPU Core Register Descriptions 5.5.2.76 Data Cache Data MSR (DC_DATA_MSR) MSR Address 00001891h Type R/W Reset Value 00000000_00000000h ...
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Bits Name Description 63:50 RSVD (RO) Reserved (Read Only). (Default = 0) 49:32 LRU Least Recently Used Value. (Default = 0) Bit 49: Ways 11-8 more recent than ways 15-12. Bit 48: Ways 7-4 more recent than ways 15-12. ...
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CPU Core Register Descriptions 5.5.2.79 Data/Instruction Cache Snoop Register (SNOOP_MSR) MSR Address 00001894h Type WO Reset Value 00000000_xxxxxxxxh The SNOOP_MSR provides a mechanism for injecting a “snoop-for-write” request into the memory subsystem. Both the I and D caches are snooped ...
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L1 Data TLB Least Recently Used MSR (L1DTLB_LRU_MSR) MSR Address 00001899h Type R/W Reset Value 00000000_00000000h ...
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CPU Core Register Descriptions 5.5.2.82 L1 Data TLB Entry MSR (L1DTLB_ENTRY_MSR) MSR Address 0000189Ah Type R/W Reset Value 00000000_00000000h ...
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L1 Data TLB Entry with Increment MSR (L1DTLB_ENTRY_I_MSR) MSR Address 0000189Bh Type R/W Reset Value 00000000_00000000h ...
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CPU Core Register Descriptions L2TLB_INDEX_MSR Bit Descriptions (Continued) Bit Name Description 15:6 RSVD (RO) Reserved (Read Only). (Default = 0) 5:0 INDEX DTE/PTE Index. Increments on every access to L2TLB_ENTRY_I_MSR (MSR 0000189Fh). 5.5.2.85 L2 TLB/DTE/PTE Least Recently Used MSR (L2TLB_LRU_MSR) ...
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L2TLB_LRU_MSR Bit Descriptions (Continued) Bits Name Description 21:16 PTE_LRU 4M PTE Least Recently Used Value. Bit 21: 4M PTE entry 0 more recent than entry 1. Bit 20: 4M PTE entry 0 more recent than entry 2. Bit 19: ...
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CPU Core Register Descriptions L2TLB_ENTRY_MSR Bit Descriptions (Continued) Bit Name Description 7 RSVD (RO) Reserved (Read Only). 6 DIRTY Dirty Flag indicates that the page has been written to. 5 ACC Accessed Flag indicates an entry ...
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L2 TLB/DTE/PTE Entry with Increment MSR (L2TLB_ENTRY_I_MSR) MSR Address 0000189Fh Type R/W Reset Value 00000000_00000000h ...
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CPU Core Register Descriptions Bits Name Description 27:24 DATA[3:0] (RO) Data Cache Data (Read Only). BIST results for data cache data arrays[3:0]. 0: Fail. 1: Pass. 23:6 RSVD (RO) Reserved (Read Only). Read RETEN_TLB L2 TLB Retention ...
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BC_CONFIG0_MSR Bit Descriptions (Continued) Bit Name Description 13 CLK_ONS CPU Core Clocks On during Suspend. 0: All CPU Core clocks off during Suspend. (Default) 1: All CPU Core clocks on during Suspend. 12 SUSP Suspend Active. Enable Suspend input. ...
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CPU Core Register Descriptions 5.5.2.92 MSR Lock MSR (MSR_LOCK_MSR) MSR Address 00001908h Type R/W Reset Value 00000000_00000000h ...
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Bit Name Description 63:0 RTSC Real Time Stamp Counter. This register is the 64-bit secondary, or “real” time stamp counter. This counter allows software to configure the TSC not to include SMM or DMM time, and still have an ...
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CPU Core Register Descriptions ...
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L2 Cache Status MSR (L2_STATUS_MSR) MSR Address 00001921h Type RO Reset Value 00000000_00000001h L2_STATUS_MSR returns the status of the L2 cache controller ...
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CPU Core Register Descriptions 5.5.2.98 L2 Cache Data MSR (L2_DATA_MSR) MSR Address 00001923h Type R/W Reset Value 00000000_00000000h L2_DATA_MSR is used to access the L2 cache data for diagnostic accesses ...
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L2 Cache Tag with Increment MSR (L2_TAG_I_MSR) MSR Address 00001925h Type R/W Reset Value 00000000_00000000h The L2_TAG_I_MSR has the auto incremented L2 cache tag, MRU and valid bits for diagnostic accesses ...
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CPU Core Register Descriptions L2_BIST_MSR Bit Descriptions (Continued) Bit Name Description 10 BIST_TAG_GO_ L2 Cache Tag BIST Way 3 Result (Read Only). WAY3 (RO) 0: Fail. (Default) 1: Pass. 9 BIST_TAG_GO_ L2 Cache Tag BIST Way 2 Result (Read Only). ...
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L2 Cache Treatment Control MSR (L2_TRTMNT_CTL_MSR) MSR Address 00001927h Type R/W Reset Value 00000000_00000000h ...
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CPU Core Register Descriptions 5.5.2.103 Power Mode MSR (PMODE_MSR) MSR Address 00001930h Type R/W Reset Value 00000000_00000300h This MSR enables some modules to turn their clocks off when they are idle to save power. Most of these bits are off ...
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Bit Name Description 63:32 BXDR1_PHYS_ Address Match Value for BXDR1. This field specifies addresses that must match the ADDR physical address currently in the bus controller in order to trigger the extended break- point. (Default = 0) 31:0 BXDR0_PHYS_ ...
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CPU Core Register Descriptions Bit Name Description BXDR7 63:60 TYPE3 Extended Breakpoint 3 Type. Selects the type of extended breakpoint 3. 0000: IM memory read (Default) 0001: DM memory read 0010: DM memory write 0011: DM memory read/write 0100: DM ...
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Bit Name Description BXDR6 31:4 RSVD Reserved Extended Breakpoint 3 Triggered Indicates that extended breakpoint 3 has trig- gered. Write to clear. (Default = Extended Breakpoint 2 Triggered Indicates that ...
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CPU Core Register Descriptions 5.5.2.108 Bus Controller Debug Register 6 MSR (BDR6_MSR) MSR Address 00001976h Type R/W Reset Value 00000000_00000000h This register contains the status of the bus controller breakpoints. When a breakpoint occurs, the corresponding status bit is set ...
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Bit Name Description 31:28 TYPE3 Breakpoint 3 Type. Selects the type of extended breakpoint 3. 0000: IM memory read (Default). 0001: DM memory read. 0010: DM memory write. 0011: DM memory read/write. 0100: DM I/O read. 0101: DM I/O ...
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CPU Core Register Descriptions 5.5.2.110 Memory Subsystem Array Control Enable MSR (MSS_ARRAY_CTL_EN_MSR) MSR Address 00001980h Type R/W Reset Value 00000000_00000000h The MSRs at addresses 00001980h-00001983h provide alternate array delay control values for the MSS arrays. After a reset, the MSS ...
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Memory Subsystem Array Control 1 MSR (MSS_ARRAY_CTL1_MSR) MSR Address 00001982h Type R/W Reset Value 00000000_104823CFh ...
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CPU Core Register Descriptions 5.5.2.114 FPU Modes MSR (FP_MODE_MSR) MSR Address 00001A00h Type R/W Reset Value 00000000_00000000h ...
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FPU x87 Control Word MSR (FPU_CW_MSR) MSR Address 00001A10h Type R/W Reset Value 00000000_00000040h ...