SAA7113HV2 NXP Semiconductors, SAA7113HV2 Datasheet
SAA7113HV2
Specifications of SAA7113HV2
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SAA7113HV2 Summary of contents
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SAA7113H 9-bit video input processor Rev. 02 — 9 May 2005 1. General description The 9-bit video input processor is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain ...
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Philips Semiconductors Line-locked system clock frequencies Digital PLL for horizontal sync processing and clock generation, horizontal and vertical sync detection Requires only one crystal (24.576 MHz) for all standards Automatic detection and 60 Hz field frequency and ...
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Philips Semiconductors 4. Quick reference data Table 1: Symbol V DDD V DDA T amb P A+D 5. Ordering information Table 2: Type number SAA7113H 9397 750 14232 Product data sheet Quick reference data Parameter Conditions digital supply voltage analog ...
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Philips Semiconductors 6. Block diagram 4 AI11 ANALOG 5 AI1D PROCESSING 7 AI12 AND 9 AOUT ANALOG-TO- 43 DIGITAL AI21 44 CONVERSION AI2D 1 AI22 AD2 AD1 6 AGND ANALOG PROCESSING CONTROL 2 V SSA1 41 V SSA2 3 V ...
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Philips Semiconductors 7. Pinning information 7.1 Pinning Fig 2. Pin configuration for QFP44 7.2 Pin description Table 3: Symbol AI22 V SSA1 V DDA1 AI11 AI1D AGND AI12 TRST AOUT V DDA0 V SSA0 9397 750 14232 Product data sheet ...
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Philips Semiconductors Table 3: Symbol VPO7 to VPO4 V SSDE1 LLC V DDDE1 VPO3 to VPO0 SDA SCL RTCO RTS0 RTS1 V SSDI V DDDI V SSDA XTAL XTALI V DDDA V DDDE2 V SSDE2 TDO TCK TDI TMS 9397 ...
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Philips Semiconductors Table 3: Symbol CE V SSA2 V DDA2 AI21 AI2D [1] For board design without boundary scan implementation connect the TRST pin to ground. [2] This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST ...
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Philips Semiconductors 8.2.1 Clamping The clamp control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect ...
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V SSA1 41 V SSA2 1 AI22 SOURCE CLAMP 44 AI2D SWITCH CIRCUIT 43 AI21 3 V DDA1 42 V DDA2 7 AI12 5 SOURCE CLAMP AI1D SWITCH CIRCUIT 4 AI11 MODE CLAMP CONTROL CONTROL HCL MODE3 MODE2 MODE1 ...
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Philips Semiconductors Fig 7. Gain flow chart 9397 750 14232 Product data sheet ANALOG INPUT AMPLIFIER ANTI-ALIAS FILTER ADC 1 NO ACTION VBLK 0 1 254 248 1/L 1/F 1/LLC2 GAIN ACCUMULATOR ...
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Philips Semiconductors Fig 8. Clamp and gain flow 8.3 Chrominance processing The 9-bit chrominance signal is fed to the multiplication inputs of a quadrature demodulator, where two subcarrier signals from the local oscillator DTO1 are applied (0 and 90 phase ...
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Philips Semiconductors The SECAM processing contains the following blocks: • Baseband ‘bell’ filters to reconstruct the amplitude and phase equalized 0 and 90 FM signals • Phase demodulator and differentiator (FM-demodulation) • De-emphasis filter to compensate the pre-emphasized input signal, ...
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Philips Semiconductors (dB) (1) CHBW[1:0] = 00. (2) CHBW[1:0] = 01. (3) CHBW[1:0] = 10. (4) CHBW[1:0] = 11. Fig 9. Chrominance filter 9397 750 14232 Product data sheet (1) 6 (2) ( ...
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LUM CHR 8 TRST 37 TCK QUADRATURE TEST 38 DEMODULATOR TDI CONTROL 39 BLOCK TMS 36 TDO SUBCARRIER GENERATION RESET 18 V DDDE1 HUEC 29 V DDDI POWER- DDDA CONTROL 34 V DDDE2 CSTD[2:0] CE CLOCKS 16 V ...
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Philips Semiconductors 8.4 Luminance processing The 9-bit luminance signal, a digital CVBS format or a luminance format (S-VHS and HI8), is fed through a switchable prefilter. High frequency components are emphasized to compensate for loss. The following chrominance trap filter ...
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Philips Semiconductors V (dB) (1) 40h. (2) 41h. (3) 42h. (4) 43h. Fig 12. Luminance control subaddress 09h, 4.43 MHz trap/CVBS mode, prefilter on and V (dB) (1) 03h. (2) 13h. (3) 23h. (4) 33h. Fig 13. Luminance control subaddress ...
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Philips Semiconductors V (dB) (1) C0h. (2) C1h. (3) C2h. (4) C3h. Fig 14. Luminance control subaddress 09h, Y/C mode, prefilter on and different aperture V (dB) (1) 80h. (2) 81h. (3) 82h. (4) 83h. Fig 15. Luminance control subaddress ...
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Philips Semiconductors V (dB) (1) 43h. (2) 53h. (3) 63h. (4) 73h. Fig 16. Luminance control subaddress 09h, 3.58 MHz trap/CVBS mode, prefilter on and V (dB) (1) 40h. (2) 41h. (3) 42h. (4) 43h. Fig 17. Luminance control subaddress ...
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Philips Semiconductors V (dB) (1) 03h. (2) 13h. (3) 23h. (4) 33h. Fig 18. Luminance control subaddress 09h, 3.58 MHz trap/CVBS mode, prefilter off and 9397 750 14232 Product data sheet (1) (2) (4) 6 (3) 18 ...
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Philips Semiconductors LUM LUMINANCE CIRCUIT CHROMINANCE PREFILTER TRAP PREF BYPS VBLB PREFILTER SYNC MACROVISION DETECTOR SYNC SLICER SYNCHRONIZATION CIRCUIT VNOI0 2 I C-BUS CONTROL VNOI1 HTC[1: C-BUS VERTICAL INTERFACE PROCESSOR 24 23 RTS0 SCL SDA Fig 19. Luminance ...
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Philips Semiconductors 8.6 Clock generation circuit The internal CGC generates all clock signals required for the video input processor. The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL the multiple of the line ...
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Philips Semiconductors 8.7 Power-on reset and CE input A missing clock, insufficient digital or analog V initiate the reset sequence; all outputs are forced to 3-state (see It is possible to force a reset by pulling the Chip Enable (CE) ...
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Philips Semiconductors Table 5: Internal power-on control sequence Directly after power-on asynchronous reset Synchronous reset sequence Status after power-on control sequence 8.8 Multistandard VBI data slicer The multistandard data slicer is a Vertical Blanking Interval (VBI) and Full Field (FF) ...
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Philips Semiconductors Table 6: Standard type US NABTS MOJI (Japanese) Japanese format switch (L20/22) 8.9 VBI-raw data bypass For a 27 MHz VBI-raw data bypass the digitized CVBS signal is upsampled after analog-to-digital conversion. Suppressing of the back folded CVBS ...
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Philips Semiconductors Table 7: Data type number [1] The number of valid bytes per line can be less for the sliced data format if standard not recognized (wrong standard or poor input ...
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Philips Semiconductors The data type selections by LCR are overruled by setting VIPB (subaddress 11h, bit 1) to logic 1. This setting is mainly intended for device production tests. The VPO-bus carries the upper or lower 8 bits of the ...
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Philips Semiconductors Table 9: Line number 261 262 263 264 and 265 266 to 282 283 284 285 to 524 525 Table 10: Line number ...
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Table 11: Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 1) Vertical line offset VOFF8 to VOFF0 = 00Ah; horizontal pixel offset HOFF10 to HOFF0 = 354h, FOFF = 1, FISET = 1 Line number (1st ...
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Table 14: Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 2) Vertical line offset VOFF8 to VOFF0 = 007h; horizontal pixel offset HOFF10 to HOFF0 = 354h, FOFF = 1, FISET = 0 Line number (1st ...
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Philips Semiconductors 255 235 128 output range Fig 23. YUV levels on the 8-bit VPO-bus (data types 6 and 15) Table 16: YUV data format on the 8-bit VPO-bus (data types ...
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Philips Semiconductors a. For sources containing 7.5 IRE black Fig 24. Raw data levels on the 8-bit VPO-bus (data type 7) Table 18: Raw data format on the 8-bit VPO-bus (data type 7) Blanking Timing reference period code ... 80 ...
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Philips Semiconductors Table 21: Name Explanation SAV SDID DC IDI1 IDI2 DLNn sliced data LOW nibble, format: NEP DLHn sliced data HIGH nibble, format: NEP EAV [1] Inverted EP (bit 7); for EP see [2] Even parity (bit 6) of ...
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Philips Semiconductors Table 22: Bit OEYC C-bus description 2 9.1 I C-bus format S SLAVE ADDRESS W Fig 25. Write procedure S SLAVE ADDRESS W Sr SLAVE ADDRESS R Fig 26. Read procedure ...
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Philips Semiconductors 2 9.2 I C-bus register description Table 24: Subaddress 00h 01h to 05h 06h to 13h 14h 15h to 17h 18h to 1Eh 1Fh 20h to 3Fh 40h to 5Eh 5Fh 60h to 62h 9397 750 14232 Product ...
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Table 25: I C-bus receiver/transmitter overview Register function Subaddress D7 (hex) Chip version (read only) 00 ID07 [1] Increment delay 01 Analog input control 1 02 FUSE1 [1] Analog input control 2 03 Analog input control 3 04 GAI17 ...
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Table 25: I C-bus receiver/transmitter overview Register function Subaddress D7 (hex) AC1 40 FISET LCR2 41 LCR02_7 LCR3 to LCR23 LCRn_7 LCR24 57 LCR24_7 FC 58 FC7 HOFF 59 HOFF7 VOFF 5A VOFF7 HVOFF 5B FOFF ...
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Philips Semiconductors 9.2.1 Subaddress 00h (read only register) Table 26: Function Chip Version (CV) 9.2.2 Subaddress 01h Table 27: Function No update Minimum delay Recommended position Maximum delay The programming of the horizontal increment delay is used to match internal ...
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Philips Semiconductors AD2 AI22 AI21 AI12 AD1 AI11 Fig 27. Mode 0; CVBS (automatic gain) AD2 AI22 AI21 AI12 AD1 AI11 Fig 29. Mode 2; CVBS (automatic gain) AD2 AI22 AI21 AI12 AD1 AI11 2 I C-bus bit BYPS (subaddress ...
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Philips Semiconductors Table 30: Analog function select FUSE Amplifier plus anti-alias filter bypassed Amplifier active Amplifier plus anti-alias filter active 9.2.4 Subaddress 03h Table 31: Function Static gain control channel 1 (GAI18) (see subaddress 04h) Sign bit of gain control ...
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Philips Semiconductors 9.2.6 Subaddress 05h Table 33: Gain control analog (AICO4); static gain control channel 2 GAI2 subaddress 05h (D7 to D0) Decimal Gain Sign bit (subaddress 03h, D1) Control bits value (dB) GAI28 0... 3 0 ...
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Philips Semiconductors 9.2.9 Subaddress 08h Table 36: Function Vertical noise reduction (VNOI) Normal mode (recommended setting) Fast mode [applicable for stable sources only; Automatic Field Detection (AUFD) must be disabled] Free running mode Vertical noise reduction bypassed Horizontal PLL (HPLL) ...
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Philips Semiconductors Table 37: Function Aperture factor = 0.5 Aperture factor = 1.0 Update time interval for analog AGC value (UPTCV) Horizontal update (once per line) Vertical update (once per field) Vertical blanking luminance bypass (VBLB) Active luminance processing Chrominance ...
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Philips Semiconductors 9.2.12 Subaddress 0Bh Table 39: Gain 1.999 (maximum) 1.109 (ITU level) 1.0 0 (luminance off) 1 (inverse luminance (inverse luminance) 1 9.2.13 Subaddress 0Ch Table 40: Gain 1.999 (maximum) 1.0 (ITU level) 0 (color off) 1 ...
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Philips Semiconductors Table 42: Function 50 Hz Fast color time constant (FCTC) Nominal time constant Fast time constant Disable chrominance comb filter (DCCF) Chrominance comb filter on (during lines determined by VREF = 1; see Chrominance comb filter permanently off ...
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Philips Semiconductors Table 44: Automatic chrominance gain control ACGC On Programmable gain via CGAIN6 to CGAIN0 9.2.17 Subaddress 10h Table 45: Luminance delay compensation (steps in 2/LLC) 4... ...0... ...3 Table 46: Control bit D3 VRLN Length Line number [1] ...
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Philips Semiconductors 9.2.18 Subaddress 11h Table 49: Function Color on (COLO) Automatic color killer Color forced on YUV decoder bypassed (VIPB) Processed data to VPO output ADC data to VPO output; dependent on mode settings Output enable real-time (OERT) RTS0, ...
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Philips Semiconductors Table 50: RTS0 output control Horizontal Lock (HL) indicator; selectable via HLSEL (subaddress 11h, bit 4) • HSEL = 0: standard horizontal lock indicator • HSEL = 1: fast horizontal lock indicator (use is not recommended for sources ...
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Philips Semiconductors Table 51: RTS1 output control 3-state, pin RTS1 is used as DOT input (see VIPB (subaddress 11h, bit reserved VIPB (subaddress 11h, bit LSBs of the 9-bit ADCs GPSW1 Horizontal Lock (HL) ...
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Philips Semiconductors 9.2.20 Subaddress 13h Table 52: Output control subaddress 13h (D7, D4, D3, D1 and D0) Function Analog test select (AOSL) AOUT connected to internal test point 1 AOUT connected to input AD1 AOUT connected to input AD2 AOUT ...
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Philips Semiconductors 9.2.22 Subaddress 16h Table 54: Stop of VGATE pulse (10-transition) Field Frame Decimal line value counting 50 Hz 1st 1 312 2nd 314 1st 2 0... 2nd 315 1st 312 ...310 2nd 625 60 Hz 1st 4 262 ...
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Philips Semiconductors Table 56 C-bus control bit HLVLN HLCK INTL 9.2.25 Subaddress 40h Table 57: Slicer set (40h) Amplitude searching Reserved 13.5 MHz (default) Reserved Reserved Table 58: Slicer set (40h) Amplitude searching Amplitude searching active (default) Amplitude ...
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Philips Semiconductors 9.2.26 Subaddresses 41h to 57h Table 62: LCR register (subaddresses 41h to 57h) WST625 CC625 VPS WSS WST525 CC525 Test line Intercast General text VITC625 Reserved NABTS Japtext JFS Active video [1] The assignment of ...
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Philips Semiconductors 9.2.28 Subaddress 59h Table 65: Slicer set (subaddresses 59h and 5Bh) Horizontal offset Recommended value 9.2.29 Subaddress 5Ah Table 66: Slicer set (subaddresses 5Ah and 5Bh) Vertical offset Minimum value 0 Maximum value 312 Value for 50 Hz ...
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Philips Semiconductors Table 71: Slicer status bit (subaddress 60h) read only VPS valid No VPS in the last frame VPS detected Table 72: Slicer status bit (subaddress 60h) read only Framing code valid No framing code in the last frame ...
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Philips Semiconductors 2 Table 75: I C-bus start setup values Subaddress Function (hexadecimal) 03 analog input control 2 04 analog input control 3 05 analog input control 4 06 horizontal sync start 07 horizontal sync stop 08 sync control 09 ...
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Philips Semiconductors 2 Table 75: I C-bus start setup values Subaddress Function (hexadecimal) 5B field offset and MSBs for horizontal and vertical offset 5C and 5D reserved 5E sliced data identification code 5F reserved 60 slicer status byte 1 61 ...
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Philips Semiconductors 11. Thermal characteristics Table 77: Thermal characteristics Symbol Parameter R thermal resistance from th(j-a) junction to ambient [1] The overall R value can vary depending on the board layout. To minimize the effective R th(j-a) connected to the ...
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Philips Semiconductors Table 78: Characteristics …continued DDD DDA Symbol Parameter Digital inputs V LOW-level input voltage on IL pins SDA and SCL pin XTALI pins ...
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Philips Semiconductors Table 78: Characteristics …continued DDD DDA Symbol Parameter Horizontal PLL f nominal line frequency permissible static deviation H Hn Subcarrier ...
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Philips Semiconductors 13. Timing diagrams CLOCK OUTPUT LLC OUTPUTS VPO, RTCO, RTS0, RTS1 Fig 35. Clock and data output timing LLC RTS1 (DOT) VPO Fig 36. DOT input timing (RTS1) 9397 750 14232 Product data sheet t LLC t f ...
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Philips Semiconductors (1) PLIN is switched to outputs RTS0 and/or RTS1 via I (2) See Fig 37. Horizontal timing diagram 9397 750 14232 Product data sheet CVBS input RAW DATA on VPO-bus 157 Y-DATA on VPO-bus RTS0/1 HREF (50 Hz) ...
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Philips Semiconductors 622 623 input CVBS RTS0/1 HREF RTS0/1 VREF (1) VRLN = 1 RTS0/1 VREF (1) VRLN = 0 RTS0/1 VS RTS0/1 ODD (3) RTS0/1 V123 (2) RTS0/1 FID 310 311 input CVBS RTS0/1 HREF RTS0/1 VREF (1) VRLN ...
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Philips Semiconductors 523 524 522 (1) (525) input CVBS RST0/1 HREF (2) VRLN = 1 RTS0/1 VREF (2) VRLN = 0 RTS0/1 VREF RTS0/1 VS RTS0/1 ODD (4) RTS0/1 V123 (3) RTS0/1 FID 260 259 261 (263) (262) (264) input ...
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Philips Semiconductors 14. Errata information 14.1 Fast H-lock indicator bit • Issue: The H-lock indicator bit (HL_FAST, available on RTS0/RTS1 and selectable with HLSEL via I function. • Impact not possible to use the signal HL_FAST as fast ...
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Philips Semiconductors 14.5 Indifferent detection of copy protected signals Detection of copy protected signals according to the Macrovision scheme (pseudo sync and AGC pulses) and thus the contents of the status information COPRO (I bit subaddress 1Fh) should ...
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Philips Semiconductors 15. Application information V DDD V DDA V SSA R10 SSA SSA SSA ...
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Philips Semiconductors a. With quartz crystal Fig 41. Oscillator application 16. Test information 16.1 Boundary scan test The SAA7113H has built-in logic and five dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The ...
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Philips Semiconductors 16.1.1 Initialization of boundary scan circuit The Test Access Port (TAP) controller should be in the reset state (TEST_LOGIC_RESET) when the the functional mode. This reset state also forces the instruction register ...
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Philips Semiconductors 17. Package outline QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 1. pin 1 index DIMENSIONS (mm are the original dimensions) A ...
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Philips Semiconductors 18. Soldering 18.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages ...
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Philips Semiconductors – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, ...
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Philips Semiconductors [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, ...
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Philips Semiconductors 20. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...
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Philips Semiconductors 25. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...
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Philips Semiconductors 24 Contact information . . . . . . . . . . . . . . . . . . . . 73 9-bit video input processor © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. ...