SAA7144 NXP Semiconductors, SAA7144 Datasheet
SAA7144
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SAA7144 Summary of contents
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... General description The SAA7144HL is a combination of four stand alone multistandard video decoders. The SAA7144HL is a pure 3 tolerant inputs and I/Os) CMOS circuit and a highly integrated circuit for video surveillance applications. All four video decoders are based on the principle of line-locked clock decoding and are able to decode the color of PAL, SECAM and NTSC signals into “ ...
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... Boundary scan test circuit complies with the “IEEE Std. 1149.b1 - 1994” Applications Surveillance application. 9397 750 14454 Product data sheet 2 C-bus controlled. Two decoder instances share one - format (8-bit) on VPO output bus B R Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Type number Package Name SAA7144HL LQFP128 9397 750 14454 Product data sheet Conditions Description plastic low profile quad flat package; 128 leads; body 14 Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor Min Typ Max 3.0 3.3 3.6 3.1 3.3 3.5 ...
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... AI11_C AI1D_C CONVERSION AI12_C AGND_C PROCESSING SCL_CD SDA_CD PROCESSING AGND_D AI12_D AI1D_D AI11_D CONVERSION PROCESSING Fig 1. Block diagram of SAA7144HL. 9397 750 14454 Product data sheet ANALOG MULTISTANDARD TEXT SLICER AND VBI DATA BYPASS ANALOG-TO- UPSAMPLING FILTER DIGITAL BYPASS AD1 UV CHROMINANCE CVBS ...
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... not connect; leave open 17 do not connect; leave open 18 analog supply voltage for the internal CGC of video decoder B Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor 102 65 001aab305 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... VPO4 of video decoder D 57 digital video output bus signal VPO3 of video decoder D Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor 2 C-bus) for instances A and B 2 C-bus) for instances A and B 2 C-bus) for instances C and D ...
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... VPO4 of video decoder B 96 supply for digital pad ring (3 ground for digital pad ring 98 do not connect; leave open Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor [1] [1] [1] [1] [1] [2] [3] © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Figure 8) show more details of the AGC. The influence of supply Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor 3. During the vertical blanking period, gain C-bus) the static gain levels for the analog © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... V DDA1(DECA) 6 AGND_A LUM This is valid for decoder and D. Here an example for decoder A is shown. Fig 6. Analog input processing using the SAA7144HL as differential front-end with 9-bit ADC (continued in Figure 10). 9397 750 14454 Product data sheet mgl065 Fig 5. Automatic gain range. ANALOG ...
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... GAIN ACCUMULATOR (18 BITS AGV FGV – system variable; VBLK = vertical blanking pulse; HSY = horizontal sync pulse; AGV = actual gain value; FGV = frozen gain value. Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor gain 9 DAC 8 LUMA/CHROMA DECODER HOLDG 1 ...
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... SBOT = sync bottom level (1). CLL = clamp level [60 Y (128 C)]. HSY = horizontal sync pulse. HCL = horizontal clamp pulse. and the values 1 (minimum) and 254 (maximum) to fulfil CCIR-601 B R Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor 0 GAIN -> HSY SBOT GAIN ...
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... The resulting signals are fed to the variable Y-delay compensation and the output interface, which contains the VPO output formatter and the output control logic; see Figure 9397 750 14454 Product data sheet 10. Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Product data sheet (1) 6 (2) ( 0.54 1.08 Transfer characteristics of the chrominance low-pass dependent on CHBW[1:0] settings. Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor mgd147 (4) (1) (3) (2) 1.62 2.16 2.7 f (MHz) © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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LUM CHR 121 TRST_N QUADRATURE 120 TCK TEST DEMODULATOR 117 CONTROL TDI BLOCK 119 TMS 118 TDO SUBCARRIER RESET GENERATION HUEC POWER- DDA0(DECA) CONTROL CSTD[2:0] CLOCK LUM This is valid for decoder and D. Here ...
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... MHz or 3.58 MHz center frequency set according to the 0 2 C-bus subaddress 09h, see 18 Y (1) 6 (2) (4) ( band-pass center frequencies. Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor Table 33) in two band-pass Figure 11 Figure 17. mgd139 (1) (2) (4) ( (MHz) Y © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... Fig 13. Luminance control SA 09h, 4.43 MHz trap, prefilter off, different aperture 9397 750 14454 Product data sheet (1) (2) (3) ( (1) (2) (4) ( band-pass center frequencies. Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor mgd140 (4) (3) (2) ( (MHz) Y mgd141 (1) (2) (4) ( (MHz) Y © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Fig 15. Luminance control SA 09h, 3.58 MHz trap, prefilter on, different aperture factors. 9397 750 14454 Product data sheet (1) (2) (4) ( band-pass center frequencies (1) (2) ( Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor mgd144 (1) (2) (4) ( (MHz) Y mgd145 (4) (3) (2) ( (MHz) Y © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Fig 16. Luminance control SA 09h, 3.58 MHz trap, prefilter off, different aperture 9397 750 14454 Product data sheet (1) (2) ( band-pass center frequencies. Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor mgd146 (1) (2) (4) ( (MHz) Y © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... DETECTOR COARSE AUFD HSB[7:0] HTC[1:0] HSS[7:0] HPLL FIDT FSEL HLCK HTC[1:0] LOOP COUNTER FILTER Figure Figure 18. Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor Y STAGE CLOCK CIRCUIT CLOCKS LINE-LOCKED CLOCK GENERATOR CLOCK DAC GENERATION CIRCUIT DISCRETE CRYSTAL TIME CLOCK OSCILLATOR ...
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... Product data sheet f (50 Hz (60 Hz). H Clock frequencies ZERO BAND PASS CROSS FC = LLC/4 DETECTION DETECTION Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor Frequency (MHz) 24.576 27 13.5 6.75 3.375 PHASE LOOP OSCILLATOR FILTER DIVIDER DIVIDER 1/2 supply voltages will start the reset ...
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... VPO7 to VPO0, SDA and LLC are in high-impedance state LLC and SDA become active; VPO7 to VPO0, are held in high-impedance state VPO7 to VPO0, are held in high-impedance state Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor POC V DDA0 DD DIGITAL POC POC RES_N LOGIC ...
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... Japtext 5 programmable Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor 2 C-bus in 2 C-bus subaddresses 41h to 57h Section 8.10. To adjust the slicers FC window Hamming check WST625 always CC625 VPS WSS ...
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... CVBS data teletext VITC/EBU time codes (Europe) VITC/SMPTE time codes (USA) reserved US NABTS MOJI (Japanese) Japanese format switch (L20/22) video component signal, active video region Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor (MHz) Section 9, subaddresses 41h to 57h). OEYC 2 ...
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... C-bus bit VBLB is set. This data type is defined for future enhancements; it could 41. Format and nominal levels are given in and Table 30, Table 31 Figure 22 and Table 18. 20. Table 27). Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor - signal, 720 active pixels per B R Figure 21 and Table 16. -C data as in active video, with two B R ...
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... SAV EAV P[3:0] reserved; evaluation not recommended (protection bits according to ITU-R BT 656 formats (data types 15 and 6) every clock cycle within this range R Table 16. Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor Table 9 and Table 10 Table 9 and Table 10 Figure 22). Table 9 ...
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... Hz vertical timing F V (ITU-R BT 656) OFTS1 = 0; OFTS0 = 0 (ITU-R BT 656 Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor OFTS1 = 0; OFTS0 = 1 OFTS1 = 1; OFTS0 = 0 VRLN = 0 VRLN = according to selected data type 1 1 via LCR2 to LCR24 1 1 (subaddresses 41h to 57h): data types 14 data 0 0 type 15 ...
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Table 11: Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 1) Vertical line offset VOFF8 to VOFF0 = 00Ah; horizontal pixel offset HOFF10 to HOFF0 = 354h, FOFF = 1, FISET = 1 Line number (1st ...
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Table 14: Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 2) Vertical line offset VOFF8 to VOFF0 = 007h; horizontal pixel offset HOFF10 to HOFF0 = 354h, FOFF = 1, FISET = 0 Line number (1st ...
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... LUMINANCE black 71 black shoulder 60 SYNC 1 sync bottom 001aac244 VBI data levels are not dependent on BCS settings. level offset (e.g. NTSC M). Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor 255 blue 100 % 240 blue 75 % 212 colorless 128 -COMPONENT C R yellow 75 % ...
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... NEP 5Eh[5:0], e. used as source identifier [1] DC Dword count: NEP but does not represent any relevant information for SAA7144HL applications. DC describes the number of succeeding 32-bit words n), where (the two data identification bytes IDI1 and IDI2) and n = number of decoded 4 bytes according to the chosen text standard ...
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... EP , bits Table 8 to Table 10 2. ACK-s SUBADDRESS ACK-s SUBADDRESS ACK-s (n bytes + acknowledge) Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor ACK-s ACK-s DATA data transferred (n bytes + acknowledge) ACK-s DATA ACK-m P data transferred mhb340 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... ACK-s ACK-m Subaddress Data LSB slave address read/write control bit order to write (the circuit is slave receiver); [1] The SAA7144HL supports the fast mode I [2] If more than one byte DATA is transmitted the subaddress pointer is automatically incremented. 2 9.2 I C-bus register description Table 23: Subaddress Description ...
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Table 24: I C-bus receiver/transmitter overview Register function Subaddress Chip version (read only) 00h Increment delay 01h Analog control 1 02h Analog control 2 03h Analog control 3 04h Reserved 05h Horizontal sync begin 06h Horizontal sync stop 07h ...
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Table 24: I C-bus receiver/transmitter overview Register function Subaddress Horizontal offset 59h Vertical offset 5Ah Horizontal offset (MSBs), vertical offset 5Bh (MSB) and field offset For testability 5Ch Reserved 5Dh Sliced data identification code 5Eh Reserved 5Fh Slicer status ...
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... LSB LSB LSB MODE[3:0] channel input selector 0000 = select CVBS (automatic gain) from AI11; see 0001 = select CVBS (automatic gain) from AI12; see XXXX = reserved; see Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor ID06 ID05 CV2 CV1 IDEL2 IDEL1 1 ...
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... MODE[3: gain is user programmable via GAI1 - not used; has to be set to logic 0 GAI18 sign bit of gain control; see Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor ADC 001aab319 Table 29 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Control bits HSS7 HSS6 HSS5 HSS4 forbidden (outside available central counter range forbidden (outside available central counter range Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor GAI13 GAI12 GAI11 GAI10 HSB3 HSB2 HSB1 HSB0 ...
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... MHz; see 11 = center frequency is 2.9 MHz; see 9397 750 14454 Product data sheet Figure 11 to Figure 16 Table note 1 Table note 1 Table note 1 Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Figure 11 to Figure 16 Control bits BRIG7 BRIG6 BRIG5 BRIG4 Control bits CONT7 CONT6 CONT5 CONT4 Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor BRIG3 BRIG2 BRIG1 BRIG0 CONT3 CONT2 CONT1 CONT0 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Control bits HUEC7 HUEC6 HUEC5 HUEC4 Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor SATN3 SATN2 SATN1 HUEC3 HUEC2 HUEC1 NTSC M (or NTSC-Japan with special level adjustment: brightness subaddress 0Ah = 95h; contrast subaddress 0Bh = 48h) PAL 4.43 (60 Hz) NTSC 4.43 (60 Hz) ...
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... Product data sheet …continued 2/LLC 2/LLC 2/LLC 2/LLC Table 41 2/LLC 2/LLC 2/LLC Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor 60 Hz Table 9 and Table 10 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... B R decoder bypassed R Table note 1 Table 44 Figure 25). Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor VREF 625 lines 0 286 first last first 24 309 23 337 622 336 Table 44 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... Product data sheet ® copy protection detection according to Macrovision Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor ® detect specification © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Bit field 1 field 2 Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor Bit Bit [1] DT3 to DT0 DT3 to DT0 0000 0000 0001 0001 0010 0010 0011 0011 0100 0100 0101 0101 ...
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... SDID[5:0] sliced data identification code; SDID[5:0] = 000000 (default) 9397 750 14454 Product data sheet Table 50 Table 49 Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Subaddress 62h 10. I C-bus start set-up The given values force the following behavior of the SAA7144HL: • The analog input AI11 expects a signal in CVBS format; analog anti-alias filter and AGC active • Automatic field detection enabled, PAL BDGHI or NTSC M standard expected • ...
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... YDEL[2: OEYC, X, VIPB, COLO ADLSB OLDSB INTL, HLVLN, FIDT, GLIMT, GLIMB, WIPA, COPRO, RDCAP FISET, HAM_N, FCE, HUNT_N, X, CLKSEL[1:0], X FC[7:0] HOFF[7:0] VOFF[7:0] FOFF VOFF8, X, HOFF[10: SDID[5:0] Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor Values (binary) Start (hexadecimal read only ...
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... FC8V, FC7V, VPSV, PPV, CCV read only -, -, F21_N, LN[8:4] LN[3:0], DT[3:0] Table 11 to Table 14 and Table 7. Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor Values (binary) Start (hexadecimal read only read only © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... SSA(all) SS(all) human body model machine model Conditions in free air = 25 C; unless otherwise specified. amb Conditions all outputs unloaded Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor Min Max 0.5 +4.6 0.5 +4.6 0 0.5 DDA (4.6 max) 0 ...
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... V (p-p), termination 18/56 and AC coupling required; coupling capacitor = 47 nF clamping current off MHz i CVBS inputs with different line frequencies outputs at 3-state SDA/SCL sink current = Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor Min Typ Max 0.5 0.7 1.4 200 - - - - ...
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... C; unless otherwise specified. amb Conditions [1] Figure Figure 26 LLC / LLC L nominal frequency 50 Hz field 60 Hz field PAL BGHIN NTSC M; NTSC Japan PAL M combination-PAL N 3rd harmonic Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor Min Typ Max 0.5 - +0.6 2 0.5 V DDD ...
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... With amplifier and anti-alias filter 9397 750 14454 Product data sheet = 25 C; unless otherwise specified. amb Conditions , t OHD;DAT PD Typical analog delay AI22 ADC(in) (ns Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor Min Typ Max - 1 3 and t . Timings and levels refer to drawings and ...
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... See Fig 27. Horizontal timing diagram. 9397 750 14454 Product data sheet LLC t LLCH t OHD;DAT VPO 28 1/LLC 157 1/LLC Table 59. Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor t LLC t LLCL burst burst processing delay CVBS- VPO sync clipped © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... DNC31 36, 123, 124, 125, 126, 127, 128 AGND AGND AGND close as possible to the IC C14 C16 100 nF 100 nF AGND AGND 3.3 V analog digital Fig 28. Application diagram of SAA7144HL. AGND AGND AGND DGND DGND C19 C21 100 nF 100 nF 100 nF 100 nF R40 R42 3.3 3 ...
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... Philips Semiconductors 15.1 Recommended printed-circuit board layout The SAA7144HL consists of analog and digital areas. Due to this special care needs to be taken for design of layout regarding crosstalk by analog and digital supply interaction recommended to use four layer Printed-Circuit Board (PCB). Top and bottom layer for signal wires, one for ground plane and one for supply plane ...
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... Test information 16.1 Boundary scan test The SAA7144HL has built-in logic and five dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7144HL follows the “IEEE Std. 1149.1 - Standard Test Access Port and Boundary - Scan Architecture” ...
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... Product data sheet Figure MSB TDI nnnn 0011010110100000 4-bit 16-bit part number version code Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor 30. LSB 00000010101 1 11-bit manufacturer identification 001aab315 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. TDO ...
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... Product data sheet scale (1) ( 0.27 0.20 20.1 14.1 22.15 16.15 0.5 0.17 0.09 19.9 13.9 21.85 15.85 REFERENCES JEDEC JEITA MS-026 Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor detail 0.75 0.81 1 0.2 0.12 0.1 0.45 0.59 ...
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... Product data sheet 2 called small/thin packages. Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor 3 350 mm so called © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... LBGA, LFBGA, SQFP, [3] , TFBGA, VFBGA, XSON , SO, SOJ [8] [9] [8] , PMFP , WQCCN.. measured in the atmosphere of the reflow oven. The package Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable suitable [5] [6] ...
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... Release date SAA7144HL_1 20050421 9397 750 14454 Product data sheet Data sheet status Change notice Product data sheet - Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor Doc. number Supersedes 9397 750 14454 - © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Trademarks Intercast — trademark of Intel Corporation. Macrovision — registered trademark of Macrovision Corporation. Rev. 01 — 21 April 2005 SAA7144HL Quadruple video input processor © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Subaddress 0Ch . . . . . . . . . . . . . . . . . . . . . . . 41 9.3.13 Subaddress 0Dh . . . . . . . . . . . . . . . . . . . . . . . 41 9.3.14 Subaddress 0Eh . . . . . . . . . . . . . . . . . . . . . . . 41 9.3.15 Subaddress 0Fh . . . . . . . . . . . . . . . . . . . . . . . 42 9.3.16 Subaddress 10h . . . . . . . . . . . . . . . . . . . . . . . 42 9.3.17 Subaddress 11h . . . . . . . . . . . . . . . . . . . . . . . 43 SAA7144HL Quadruple video input processor 9.3.18 Subaddress 13h . . . . . . . . . . . . . . . . . . . . . . . 43 9.3.19 Subaddress 1Fh (read only register 9.3.20 Subaddress 40h . . . . . . . . . . . . . . . . . . . . . . . 44 9.3.21 Subaddresses 41h to 57h . . . . . . . . . . . . . . . 45 9.3.22 Subaddress 58h . . . . . . . . . . . . . . . . . . . . . . . 45 9 ...