IP-POSPHY/L3 Altera, IP-POSPHY/L3 Datasheet
IP-POSPHY/L3
Specifications of IP-POSPHY/L3
Related parts for IP-POSPHY/L3
IP-POSPHY/L3 Summary of contents
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... The IP described in this document is scheduled for product obsolescence and discontinued support as described in PDN0906. Therefore, Altera recommend use of this IP in new designs. For more information about Altera’s current IP offering, refer to Altera’s 101 Innovation Drive San Jose, CA 95134 www.altera.com POS-PHY Level 2 and 3 Compiler Intellectual Property website ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation ...
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... Launch IP Toolbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Step 1: Parameterize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 Step 2: Set Up Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9 Step 3: Generate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10 Simulate the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12 IP Functional Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13 Testbench with the ModelSim Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13 Testbench with NativeLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13 Compile the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15 Program a Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15 Set Up Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16 Chapter 3. Functional Description Example Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3– ...
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... Atlantic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–26 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–29 Signal Naming Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–30 Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–31 Example Packet Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–31 MegaCore Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–31 Additional Information Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 POS-PHY Level 2 and 3 Compiler User Guide © November 2009 Altera Corporation Preliminary ...
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... MegaCore IP Library Release Notes function. The MegaCore IP Library Release Notes ® Preliminary POS-PHY Level 2 and ® Description 9.1 November 2009 IP-POSPHY/P2 IP-POSPHY/L2 IP-POSPHY/P3 IP-POSPHY/L3 0058 0071 0070 0071 0051 0071 0050 0071 6AF7 II software compiles the ® POS-PHY Level 2 and 3 Compiler User Guide ...
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... Configurable first-in first-out (FIFO) options: selectable FIFO width, depth, and fill ■ thresholds. ■ Easy-to-use IP Toolbench interface ■ IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators ■ Support for OpenCore Plus evaluation POS-PHY Level 2 and 3 Compiler User Guide Device Family ...
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... SONET/SDH (POS) devices using the standard POS-PHY bus. The POS-PHY Level 2 and 3 Compiler comprises separately configurable modules, which can be easily combined via the IP Toolbench to generate a highly parameterized module, allowing POS-PHY compliant interfaces (and non-standard interfaces included in custom designs. ...
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... MegaCore Level 2/3 Function PHY/Link Interface Level 2/3 Level 2/3 PHY/Link PHY/Link Interface Interface MPHY Level 2/3 PHY/Link Interface Preliminary Chapter 1: About This Compiler General Description Link SPHY PHY SPHY PHY SPHY SPHY FS 13: Atlantic Interface. SM © November 2009 Altera Corporation ...
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... MPHY 4-port transmit Table 1–5. Performance—POS-PHY Level 2 PHY Layer—Cyclone II Device (Part MegaCore Function Device: EP2C5F256C6 SPHY receive © November 2009 Altera Corporation “OpenCore Plus Time-Out Behavior” on page 3–6 Megafunctions. 1–7 show typical expected performance for SPHY and 4-port POS- ...
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... Memory Blocks Logic ALUTs Registers M9K 149 330 164 313 522 1,019 613 1,009 © November 2009 Altera Corporation Preliminary Chapter 1: About This Compiler f (MHz) MAX 159 161 139 f (MHz) MAX 2 340 2 346 8 318 8 293 ...
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... SPHY transmit MPHY 4-port receive MPHY 4-port transmit Table 1–12. Performance—POS-PHY Level 3 PHY Layer—Stratix IV Device MegaCore Function SPHY receive SPHY transmit MPHY 4-port receive MPHY 4-port transmit © November 2009 Altera Corporation Memory Blocks LEs M4K 350 2 365 2 1,175 ...
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... POS-PHY Level 2 and 3 Compiler User Guide Performance and Resource Utilization © November 2009 Altera Corporation Preliminary Chapter 1: About This Compiler ...
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... Contains the Altera MegaCore IP Library and third-party IP cores. altera Contains the Altera MegaCore IP Library. 2. Create a custom variation of a POS-PHY Level MegaCore function using IP Toolbench Toolbench is a toolbar from which you can quickly and easily view documentation, specify parameters, and generate all of the files necessary for integrating the parameterized MegaCore function into your design. © ...
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... Perform design verification. POS-PHY Level 2 & 3 Walkthrough This walkthrough explains how to create a POS-PHY Level MegaCore function using the Altera POS-PHY Level 2 and 3 Compiler IP Toolbench and the Quartus II software. When you finish generating a POS-PHY Level MegaCore function, you can incorporate it into your overall project. ...
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... The remaining pages in the New Project Wizard are optional. Click Finish to complete the Quartus II project. You have finished creating your new Quartus II project. Launch IP Toolbench To launch IP Toolbench in the Quartus II software, follow these steps: 1. Start the MegaWizard Manager (Tools menu). The MegaWizard Plug-In Manager dialog box displays. 1 Refer to the Quartus II Help for more information on how to use the MegaWizard Plug-In Manager ...
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... New Project Wizard. Append a variation name for the MegaCore function output files <project path>\<variation name>. made these settings. Figure 2–3. Select the Megafunction 6. Click Next to launch IP Toolbench. POS-PHY Level 2 and 3 Compiler User Guide POS-PHY Level 2 & 3 Walkthrough Figure 2–3 shows the wizard after you have © ...
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... In a MPHY architecture there is a ‘B’ interface for each supported channel (maximum eight). Select the number of supported channels that you require create a design that supports source and sink data directions, you must run IP Toolbench twice, to create the source and sink designs separately. © November 2009 Altera Corporation Figure 2–4 on page Figure 2– ...
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... POS-PHY level 2. 1 The Atlantic interface can be 8-, 16-, 32-, or 64-bits wide. Figure 2–7. Choose the Interface Settings POS-PHY Level 2 and 3 Compiler User Guide POS-PHY Level 2 & 3 Walkthrough Figure 2–6). Figure 2–7 on page 2–6). © November 2009 Altera Corporation Preliminary Chapter 2: Getting Started ...
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... If you select the Fixed Burst option, you must also set the burst size by entering a value in the Burst field. Data is then sent in bursts of the specified burst size only bursts containing an end of packet. © November 2009 Altera Corporation Figure 2–8). “Parity Settings” on page ...
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... The maximum value is derived from the empty threshold. It must take into ■ account the latency in the pipeline and the time that the core takes to decide to stop sending data. Therefore, the maximum burst size is calculated as follows: (‘A’ interface empty threshold in bytes) – (5 × fifo_byte_width) Where fifo_byte_width is the width in bytes of the FIFO (4 for a 32-bit data width) ...
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... Figure 2–11. Product Order Code Step 2: Set Up Simulation An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model produced by the Quartus II software. It allows for fast functional simulation of IP using industry-standard VHDL and Verilog HDL simulators. c You may only use these simulation model output files for simulation purposes and expressly not for synthesis or any other purposes ...
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... MegaCore function. If your synthesis tool supports this feature, turn on Generate netlist. 5. Click OK. Step 3: Generate To generate your MegaCore function, follow these steps: 1. Click Step 3: Generate in IP Toolbench (see POS-PHY Level 2 and 3 Compiler User Guide POS-PHY Level 2 & 3 Walkthrough Figure 2–14). ...
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... Figure 2–14. IP Toolbench—Generate Figure 2–15 on page 2–11 Figure 2–15. Generation Report Table 2–1 directory. The names and types of files specified in the IP Toolbench report vary based on whether you created your design with VHDL or Verilog HDL. © November 2009 Altera Corporation shows the generation report. ...
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... The Quartus II IP File (.qip file generated by the MegaWizard interface or SOPC Builder that contains information about a generated IP core. You are prompted to add this .qip file to the current Quartus II project at the time of file generation. In most cases, the .qip file contains all of the necessary assignments and information required to process the core or system in the Quartus II compiler ...
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... NativeLink. f For more information on NativeLink, refer to the Simulation Tools Testbench with the ModelSim Simulator To use an example testbench with IP functional simulation models in the ModelSim simulator, follow these steps: 1 The testbench includes pregenerated Verilog HDL IP functional simulation models. 1. Start the ModelSim simulator. ...
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... POS-PHY Level 2 and 3 Compiler User Guide (see also Figure 2–16 on page 2–15). To enter the files described in the Parameter <any name> auk_pac_mrx_ref mrx 100 ns auk_pac_mrx_ref_tb.v shows the testbench settings for a receive simulation. Preliminary Chapter 2: Getting Started Simulate the Design Setting/File Name (1) (1) (2) © November 2009 Altera Corporation ...
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... With Altera's free OpenCore Plus evaluation feature, you can evaluate the POS-PHY Level 2 and 3 Compiler before you purchase a license. OpenCore Plus evaluation allows you to generate an IP functional simulation model, and produce a time-limited programming file. f For more information on IP functional simulation models, refer to the ...
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... After you purchase a license for the POS-PHY Level 2 and 3 MegaCore function, you can request a license file from the Altera website at install it on your computer. When you request a license file, Altera emails you a license.dat file. If you do not have Internet access, contact your local Altera representative ...
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... A MegaCore function must have a minimum of one source and one sink interface. Figure 3–1. Example MegaCore Function Interfaces © November 2009 Altera Corporation 3. Functional Description Table 3–1 shows the possible interfaces. ‘A’ Interface 3– ...
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... Function Interface Source PHY Receive Interface Function shows a packet-processing function, which receives packets at Atlantic Atlantic Interfaces Interfaces Packet Processing Function Preliminary Chapter 3: Functional Description Example Configurations 'B1' Sink Interface 'B2' Sink Interface 'B3' Sink Interface ' Sink Interface Source Link Transmit Interface Function Link Receive ...
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... Chapter 3: Functional Description Example Implementations Figure 3–5 shows a bridging function with multiple lower-rate ports, which can be 8- bit POS-PHY level 3 or 16-bit POS-PHY level 2. Figure 3–5. Example Configuration 2—POS-PHY Bridging Functions Figure 3–6 on page 3–3 an MPHY POS-PHY level 2 interface and one first-in first-out (FIFO) buffer per supported address (MPHY). Figure 3– ...
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... POS-PHY Level 2 and 3 Compiler User Guide Atlantic Interfaces FPGA MegaCore Function 1 Level 3 Link Interface (Source) User Logic MegaCore Function 1 Level 3 Link Interface (Sink) shows the FPGA interfacing multiple POS-PHY level 2 devices Level 2 FIFO Link Interface Level 2 Link FIFO Interface Level 3 PHY Interface Level 2 ...
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... POS-PHY Interface Each POS-PHY supports single and multi-PHY implementations. The POS-PHY interface interfaces to an internal multiplexer, which allows access to multiple/single internal packet FIFO buffers. Status information from the FIFO buffers is used to control the POS-PHY interface. The source interface provides polled or direct packet available modes. © ...
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... POS-PHY to or from an 8-bit POS-PHY. Atlantic interfaces here can be a master or a slave interfaces. 4. After a POS-PHY interface—where you can create a POS-PHY bridge. From a single compiler you can build a MPHY to multiple SPHY bridge SPHY to SPHY bridge. You can create more complex solutions by instantiating more than one MegaCore function. ...
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... The data_outA output goes low ■ f For more information on OpenCore Plus hardware evaluation, see Evaluation” on page 1–4 Parameters The function’s parameters, which can only be set in IP Toolbench (see Parameterize” on page Interface Settings ■ Parity Settings ■ ■ ...
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... For a sink Atlantic interface, the par pin is an input that sees either a one or a zero depending on the incoming data’s parity value. POS-PHY Level 2 and 3 Compiler User Guide Data Width Out Number of Errors Generated per Input Error Preliminary Chapter 3: Functional Description Parameters © November 2009 Altera Corporation ...
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... Chapter 3: Functional Description Parameters If a parity error is detected on a sink interface port, which has a wider data width than its corresponding source interface port, the parity output is high on all output words that correspond to the input word with an error (see When a parity error is detected (as the data comes in), but the data width changes (increases), there are two options— ...
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... PTPA and STPA inputs. Not applicable in SPHY mode. When operating in direct status mode, this is indicated using the DTPA inputs. This should be set to the — minimum value allowed. © November 2009 Altera Corporation Preliminary Chapter 3: Functional Description Parameters FIFO Remote Burst ...
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... Chapter 3: Functional Description Parameters Table 3–3. POS-PHY Level 3 FIFO Buffer Settings (Part Interface (Direction) FIFO Threshold PHY When there is more than or equal Transmit to FIFO buffer threshold spaces for (Sink) bytes in any of its FIFO buffers (1 FIFO buffer per channel), the interface indicates this on a per channel basis to the link transmit interface ...
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... When operating in polled mode, this is detected using the PRPA input. When operating in direct status mode, this is detected using the DRPA inputs. POS-PHY Level 2 and 3 Compiler User Guide Chapter 3: Functional Description FIFO Burst Indicates the maximum number of bytes the interface transfers in each FIFO buffer burst. ...
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... Chapter 3: Functional Description Parameters Table 3–4. POS-PHY Level 2 FIFO Buffer Settings (Part Interface (Direction) FIFO Threshold PHY When there is more than or equal to FIFO Transmit buffer threshold spaces for bytes in any of (Sink) its FIFO buffers (1 FIFO buffer per channel), the interface indicates this on a per channel basis to the link transmit interface ...
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... Slave has no data Figure 3–13 shows the behavior of the dav signal. FIFO 1 dav 0 Full Burst threshold threshold Figure 3–14 shows the behavior of the dav signal. FIFO 1 dav 0 Burst Empty threshold threshold Preliminary Chapter 3: Functional Description Parameters (Note 1) © November 2009 Altera Corporation ...
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... Chapter 3: Functional Description Parameters FIFO Buffer Size The FIFO buffer size is automatically set wide as the widest of the input and the output port. Each word in the FIFO buffer can only contain at most one packet. Where the FIFO buffer width is N bytes, packets bytes in length occupy 1 FIFO buffer word. ...
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... MegaCore function uses radr and prpa to support all channels. In the POS-PHY transmit direction the MegaCore function uses tadr and ptpa pins to support all channels. The stpa signal is removed from the MegaCore function. Preliminary Chapter 3: Functional Description Interface Signals © November 2009 Altera Corporation ...
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... Deasserting the resets must be done synchronously to its clock domain. Additionally, IP Toolbench can connect the independent resets and clocks to a common reset and clock (see ‘A’ interface signals are prefixed by a_; ‘B’ interface signals are prefixed by b1_, b2_, and so on ...
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... When tmod[1:0] = ‘01’ tdat[31:8] is valid. When tmod[1:0] = ‘10’ tdat[31:16] is valid. When tmod[1:0] = ‘11’ tdat[31:24] is valid. When tmod[1:0] should only be asserted when teop is asserted. POS-PHY Level 2 and 3 Compiler User Guide Chapter 3: Functional Description Description © November 2009 Altera Corporation Preliminary Interface Signals ...
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... Chapter 3: Functional Description Interface Signals Table 3–9. POS-PHY Level 3 Transmit Interface (Part Signal Direction Link to PHY Transmit write enable. tenb controls the flow of data to the transmit FIFO buffers. tenb When tenb is high, tdat, tmod, tsop, teop and terr are invalid and are ignored by the PHY-layer ...
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... When renb is sampled low by the PHY device, a read is not performed and rdat, rprty, rmod, rsop, reop, rerr, rsx, and rval are not updated on the following rising edge of rfclk. Preliminary Chapter 3: Functional Description Interface Signals © November 2009 Altera Corporation ...
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... Chapter 3: Functional Description Interface Signals Table 3–10. POS-PHY Level 3 Receive Interface (Part Signal Direction PHY to link rval PHY to link rsx Figure 3–16 shows the renb signal behavior. © November 2009 Altera Corporation Description Receive data valid. rval indicates the validity of the receive data signals. rval transitions low when a receive FIFO buffer is empty or at the end of a packet ...
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... Table 3–11 describes the POS-PHY level 2 transmit interface. POS-PHY Level 2 and 3 Compiler User Guide rfclk renb (1) (2) (3) Preliminary Chapter 3: Functional Description Interface Signals (4) (5) (6) © November 2009 Altera Corporation ...
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... Chapter 3: Functional Description Interface Signals Table 3–11. POS-PHY Level 2 Transmit Interface (Part Signal Direction Link to PHY Transmit packet data bus. tdat carries the packet octets that are written to the tdat[15/7:0] (1) Link to PHY Transmit bus parity. tprty indicates the parity calculated over the whole tdat tprty Link to PHY The transmit word modulo ...
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... FIFO buffer is not full. When dtpa[x] transitions low, it indicates that the transmit FIFO buffer has reached fifo_threshold words. transactions from the link-layer device to the PHY-layer device. tfclk can cycle at any rate from 25 MHz MHz. Description Preliminary Chapter 3: Functional Description Interface Signals © November 2009 Altera Corporation ...
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... Chapter 3: Functional Description Interface Signals Table 3–12. POS-PHY Level 2 Receive Interface (Part Signal Direction PHY to link The receive word modulo signal. rmod indicates the size of the current word. rmod is rmod (2) only used during the last word transfer of a packet, when reop is asserted. During a packet transfer every word must be complete except the last word, which can be composed bytes ...
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... For further information on the Atlantic interface, refer to the Atlantic Interface Functional Specification. Figure 3–17 shows the following two Atlantic interface control options (and all four interface types): ■ Master source to slave sink POS-PHY Level 2 and 3 Compiler User Guide Chapter 3: Functional Description Description © November 2009 Altera Corporation Preliminary Interface Signals ...
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... Chapter 3: Functional Description Interface Signals ■ Master sink to slave source The data flow on the Atlantic interface can be in either direction. Figure 3–17. Atlantic Interface Control Options Note to Figure 3–17: (1) Buses are unidirectional only. A slave sink responds to write commands from the master source and behaves like a synchronous FIFO buffer ...
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... A 32-bit dat bus requires a mty[1:0] signal A 64-bit dat bus requires a mty[2:0] signal mty can only be non-zero when eop is asserted. Table 3–14 shows the Atlantic control interface signal definitions. POS-PHY Level 2 and 3 Compiler User Guide Chapter 3: Functional Description Description © November 2009 Altera Corporation Preliminary Interface Signals ...
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... Ensure that the Atlantic slave source logic is reset while the MegaCore function is in reset. ■ Drive the bN_dav input signal from a flip-flop reset by bN_reset_n and fed by your desired dav signal. ■ Data valid. Present only on a slave source and master sink interface. When high, val indicates valid data val signals ...
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... Master source begins writing data to the slave sink. (7) Slave sink indicates it still has space, but the master source has run out of data. Signal Naming Convention When you include an Atlantic interface in a design, the IP Toolbench generates the signal names, which are prefixed by <port name>_, such as, b1_ena, b1_val, b2_ena, b2_val. ...
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... The POS-PHY Level 2 and 3 Compiler has also been verified for interworking with simulation models for two PMC-Sierra chips. The PM5351 uses a POS-PHY level 2, 4- channel, PHY interface and was tested by connecting a POS-PHY level 2 link interface (configured by the POS-PHY Level 2 and 3 Compiler). The PM7325 uses a POS-PHY ...
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... POS-PHY Level 2 and 3 Compiler User Guide Chapter 3: Functional Description © November 2009 Altera Corporation Preliminary MegaCore Verification ...
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... No changes. May 2008 8.0 Added support for Stratix ■ Updated ■ Corrected ■ October 2007 7.2 Improved desciption of May 2007 7.1 Updated the device support ■ Improved ■ December 2006 7.0 Updated the device support. December 2006 6.1 Updated the release information ■ ...
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... Active-low signals are denoted by suffix n. Example: resetn. . Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf. Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI) ...