IPPOSPHYL2 Altera, IPPOSPHYL2 Datasheet

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... The IP described in this document is scheduled for product obsolescence and discontinued support as described in PDN0906. Therefore, Altera recommend use of this IP in new designs. For more information about Altera’s current IP offering, refer to Altera’s 101 Innovation Drive San Jose, CA 95134 www.altera.com POS-PHY Level 2 and 3 Compiler Intellectual Property website ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation ...

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... Example Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 Example Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3 Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4 POS-PHY Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5 Packet Data Width Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6 Packet FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6 ‘B’ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6 OpenCore Plus Time-Out Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6 © November 2009 Altera Corporation POS-PHY Level 2 and 3 Compiler User Guide Preliminary Contents ...

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... Atlantic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–26 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–29 Signal Naming Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–30 Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–31 Example Packet Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–31 MegaCore Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–31 Additional Information Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 POS-PHY Level 2 and 3 Compiler User Guide © November 2009 Altera Corporation Preliminary ...

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... Altera does not verify compilation with MegaCore function versions older than one release." Device Family Support MegaCore functions provide either full or preliminary support for target Altera device families: ■ Full support means the MegaCore function meets all functional and timing requirements for the device family and may be used in production designs ■ ...

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... Configurable first-in first-out (FIFO) options: selectable FIFO width, depth, and fill ■ thresholds. ■ Easy-to-use IP Toolbench interface ■ IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators ■ Support for OpenCore Plus evaluation POS-PHY Level 2 and 3 Compiler User Guide Device Family ...

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... The compiler allows configurations such as PHY-PHY, link-link bridges, or packet multiplexing MegaCore functions, and SPHY and MPHY applications. page 1–3 shows the possible interfaces. bridges. Figure 1–1. Interfaces © November 2009 Altera Corporation Figure 1–2 on page 1–4 MegaCore Function PHY Atlantic Interface ...

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... Figure 1–2. Bridges Atlantic Interface The Atlantic interface allows a consistent interface between all Altera cell and packet MegaCore functions. The Atlantic interface supports a point-to-point connection. f For more information on the Atlantic interface, refer to OpenCore Plus Evaluation With Altera's free OpenCore Plus evaluation feature, you can perform the following ...

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... MPHY 4-port transmit Table 1–5. Performance—POS-PHY Level 2 PHY Layer—Cyclone II Device (Part MegaCore Function Device: EP2C5F256C6 SPHY receive © November 2009 Altera Corporation “OpenCore Plus Time-Out Behavior” on page 3–6 Megafunctions. 1–7 show typical expected performance for SPHY and 4-port POS- ...

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... Memory Blocks Logic ALUTs Registers M9K 149 330 164 313 522 1,019 613 1,009 © November 2009 Altera Corporation Preliminary Chapter 1: About This Compiler f (MHz) MAX 159 161 139 f (MHz) MAX 2 340 2 346 8 318 8 293 ...

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... SPHY transmit MPHY 4-port receive MPHY 4-port transmit Table 1–12. Performance—POS-PHY Level 3 PHY Layer—Stratix IV Device MegaCore Function SPHY receive SPHY transmit MPHY 4-port receive MPHY 4-port transmit © November 2009 Altera Corporation Memory Blocks LEs M4K 350 2 365 2 1,175 ...

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... POS-PHY Level 2 and 3 Compiler User Guide Performance and Resource Utilization © November 2009 Altera Corporation Preliminary Chapter 1: About This Compiler ...

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... For system requirements and installation instructions, refer to Installation & Licensing for Windows and Linux Figure 2–1 on page 2–1 PHY Level 2 and 3 Compiler, where <path> is the installation directory. The default installation directory on Windows is c:\altera\90; on Linux it is /opt/altera90. Figure 2–1. Directory Structure <path> Installation directory. ...

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... Perform design verification. POS-PHY Level 2 & 3 Walkthrough This walkthrough explains how to create a POS-PHY Level MegaCore function using the Altera POS-PHY Level 2 and 3 Compiler IP Toolbench and the Quartus II software. When you finish generating a POS-PHY Level MegaCore function, you can incorporate it into your overall project. ...

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... Chapter 2: Getting Started POS-PHY Level 2 & 3 Walkthrough 1. Choose Programs > Altera > Quartus II <version> (Windows Start menu) to run the Quartus II software. Alternatively, you can also use the Quartus II Web Edition software. 2. Choose New Project Wizard (File menu). 3. Click Next in the New Project Wizard Introduction page (the introduction does not display if you turned it off previously) ...

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... Figure 2–3. Select the Megafunction 6. Click Next to launch IP Toolbench. POS-PHY Level 2 and 3 Compiler User Guide POS-PHY Level 2 & 3 Walkthrough Figure 2–3 shows the wizard after you have © November 2009 Altera Corporation Preliminary Chapter 2: Getting Started ...

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... Select the number of supported channels that you require create a design that supports source and sink data directions, you must run IP Toolbench twice, to create the source and sink designs separately. © November 2009 Altera Corporation Figure 2–4 on page Figure 2–5). ...

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... POS-PHY level 2. 1 The Atlantic interface can be 8-, 16-, 32-, or 64-bits wide. Figure 2–7. Choose the Interface Settings POS-PHY Level 2 and 3 Compiler User Guide POS-PHY Level 2 & 3 Walkthrough Figure 2–6). Figure 2–7 on page 2–6). © November 2009 Altera Corporation Preliminary Chapter 2: Getting Started ...

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... If you select the Fixed Burst option, you must also set the burst size by entering a value in the Burst field. Data is then sent in bursts of the specified burst size only bursts containing an end of packet. © November 2009 Altera Corporation Figure 2–8). “Parity Settings” on page ...

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... Click Next. 15. IP Toolbench shows the product order codes (see POS-PHY Level 2 and 3 Compiler User Guide POS-PHY Level 2 & 3 Walkthrough “FIFO Buffer Settings” on Figure 3–15. Figure 2–11). Click Finish. © November 2009 Altera Corporation Preliminary Chapter 2: Getting Started 2–10). “Address & ...

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... To generate an IP functional simulation model for your MegaCore function, follow these steps: 1. Click Set Up Simulation in IP Toolbench (see Figure 2–12. IP Toolbench—Set Up Simulation 2. Turn on Generate Simulation Model (see © November 2009 Altera Corporation Figure 2–12 on page Figure 2–13). POS-PHY Level 2 and 3 Compiler User Guide Preliminary 2– ...

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... Generate netlist. 5. Click OK. Step 3: Generate To generate your MegaCore function, follow these steps: 1. Click Step 3: Generate in IP Toolbench (see POS-PHY Level 2 and 3 Compiler User Guide POS-PHY Level 2 & 3 Walkthrough Figure 2–14). © November 2009 Altera Corporation Preliminary Chapter 2: Getting Started ...

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... The names and types of files specified in the IP Toolbench report vary based on whether you created your design with VHDL or Verilog HDL. © November 2009 Altera Corporation shows the generation report. describes the generated files and other files that may be in your project Preliminary 2– ...

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... Tools chapter in volume 3 of the Quartus II Handbook. Altera also provides fixed example VHDL and Verilog HDL testbenches that you can use to simulate example sink or source POS-PHY systems. You can use a testbench as a basis for your own design. The testbenches can be used with the IP functional simulation models ...

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... On the Assignments menu click Settings. b. Under Category click Libraries c. In Project library name click ... d. Browse to \pos_phy_l2l3\lib and click Open. e. Click Add. f. Click OK. © November 2009 Altera Corporation Simulating Altera IP in Third-Party chapter in volume 3 of the Quartus II Handbook. Preliminary 2–13 POS-PHY Level 2 and 3 Compiler User Guide ...

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... POS-PHY Level 2 and 3 Compiler User Guide (see also Figure 2–16 on page 2–15). To enter the files described in the Parameter <any name> auk_pac_mrx_ref mrx 100 ns auk_pac_mrx_ref_tb.v shows the testbench settings for a receive simulation. Preliminary Chapter 2: Getting Started Simulate the Design Setting/File Name (1) (1) (2) © November 2009 Altera Corporation ...

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... You can use the Quartus II software to compile your design. Refer to Quartus II Help for instructions on compiling your design. Program a Device After you have compiled your design, program your targeted Altera device, and verify your design in hardware. With Altera's free OpenCore Plus evaluation feature, you can evaluate the POS-PHY Level 2 and 3 Compiler before you purchase a license ...

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... After you purchase a license for the POS-PHY Level 2 and 3 MegaCore function, you can request a license file from the Altera website at install it on your computer. When you request a license file, Altera emails you a license.dat file. If you do not have Internet access, contact your local Altera representative ...

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... A MegaCore function must have a minimum of one source and one sink interface. Figure 3–1. Example MegaCore Function Interfaces © November 2009 Altera Corporation 3. Functional Description Table 3–1 shows the possible interfaces. ‘A’ Interface 3– ...

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... Preliminary Chapter 3: Functional Description Example Configurations 'B1' Sink Interface 'B2' Sink Interface 'B3' Sink Interface ' Sink Interface Source Link Transmit Interface Function Link Receive Sink Interface Function MegaCore Function 2 FIFO 100 MHz Level 3 32 bit FIFO PHY Interface FIFO © November 2009 Altera Corporation ...

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... MPHY POS-PHY level 2 interface and one first-in first-out (FIFO) buffer per supported address (MPHY). Figure 3–6. Example Configuration 3—MPHY to MPHY Bridge Example Implementations Figure 3–7 shows the FPGA interfacing to an OC-48 framer. © November 2009 Altera Corporation MegaCore Function 1 FIFO 100 MHz Level 3 32 bit ...

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... FIFO Interface Level 3 PHY Interface Level 2 FIFO Link Interface Level 2 FIFO Link Interface Preliminary Chapter 3: Functional Description Internal Architecture PHY OC48 Framer PHY Level 2 PHY Device Level 2 PHY Device Level 2 PHY Device Level 2 PHY Device 'B' Interface © November 2009 Altera Corporation ...

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... FIFO buffers. Status information from the FIFO buffers is used to control the POS-PHY interface. The source interface provides polled or direct packet available modes. © November 2009 Altera Corporation shows the sink MegaCore function block diagram. Packet Data Packet Data ...

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... For MegaCore functions, the untethered timeout is 1 hour; the tethered timeout value is indefinite. Your design stops working after the hardware evaluation time expires and the following events occur: POS-PHY Level 2 and 3 Compiler User Guide Chapter 3: Functional Description OpenCore Plus Time-Out Behavior © November 2009 Altera Corporation Preliminary ™ ...

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... MegaCore function with an Atlantic slave interface ■ A Clock—the corresponding ‘B’ interface uses an internal single clock FIFO buffer, and is clocked by the A interface clock pin © November 2009 Altera Corporation and AN 320: OpenCore Plus Evaluation of 2–5), include the following settings: ...

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... For a sink Atlantic interface, the par pin is an input that sees either a one or a zero depending on the incoming data’s parity value. POS-PHY Level 2 and 3 Compiler User Guide Data Width Out Number of Errors Generated per Input Error Preliminary Chapter 3: Functional Description Parameters © November 2009 Altera Corporation ...

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... FIFO Buffer Settings Table 3–3 shows the effect of the FIFO buffer settings for POS-PHY level 3 interfaces. 1 All FIFO buffer parameters are shown in bytes. © November 2009 Altera Corporation Table 3–2). POS-PHY Level 2 and 3 Compiler User Guide Preliminary 3–9 ...

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... PTPA and STPA inputs. Not applicable in SPHY mode. When operating in direct status mode, this is indicated using the DTPA inputs. This should be set to the — minimum value allowed. © November 2009 Altera Corporation Preliminary Chapter 3: Functional Description Parameters FIFO Remote Burst ...

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... RENB input. Table 3–4 shows the effect of the FIFO buffer settings for POS-PHY level 2 interfaces. © November 2009 Altera Corporation FIFO Burst When there is less than FIFO — buffer burst spaces for bytes ...

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... Set FIFO buffer burst <= FIFO buffer threshold. In SPHY mode, this should be set to the minimum value allowed. © November 2009 Altera Corporation Preliminary Parameters FIFO Remote Burst When the interface is in the process of transferring data and the ...

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... Note to Figure 3–11: (1) The slave asserts dav high for two reasons: it has passed its threshold EOP has occurred. © November 2009 Altera Corporation FIFO Burst When there is less than FIFO buffer burst spaces for bytes in any of its FIFO buffers (1 FIFO buffer per ...

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... Slave has no data Figure 3–13 shows the behavior of the dav signal. FIFO 1 dav 0 Full Burst threshold threshold Figure 3–14 shows the behavior of the dav signal. FIFO 1 dav 0 Burst Empty threshold threshold Preliminary Chapter 3: Functional Description Parameters (Note 1) © November 2009 Altera Corporation ...

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... POS-PHY Level 2 Interfaces The POS-PHY level 2 interfaces can be multi- or single-channel. multi-channel packet available mode options. © November 2009 Altera Corporation Description In the POS-PHY transmit direction the MegaCore function uses one dtpa pin per supported channel. In the POS-PHY receive direction the MegaCore function uses renb and rval to support all channels ...

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... MegaCore function uses radr and prpa to support all channels. In the POS-PHY transmit direction the MegaCore function uses tadr and ptpa pins to support all channels. The stpa signal is removed from the MegaCore function. Preliminary Chapter 3: Functional Description Interface Signals © November 2009 Altera Corporation ...

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... POS-PHY Level 3 Interface The interface direction is shown as either link to PHY, or PHY to link. For a POS-PHY level 3 link-layer MegaCore function, the following rules apply: © November 2009 Altera Corporation bit FIFO ...

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... When tmod[1:0] = ‘01’ tdat[31:8] is valid. When tmod[1:0] = ‘10’ tdat[31:16] is valid. When tmod[1:0] = ‘11’ tdat[31:24] is valid. When tmod[1:0] should only be asserted when teop is asserted. POS-PHY Level 2 and 3 Compiler User Guide Chapter 3: Functional Description Description © November 2009 Altera Corporation Preliminary Interface Signals ...

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... PHY device. ptpa is required if packet-level transfer mode is supported. ptpa is updated on the rising edge of tfclk. Notes to Table 3–9: (1) Packet-level mode only (2) Byte-level mode only Table 3–10 describes the POS-PHY level 3 receive interface. © November 2009 Altera Corporation Description POS-PHY Level 2 and 3 Compiler User Guide Preliminary 3–19 ...

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... When renb is sampled low by the PHY device, a read is not performed and rdat, rprty, rmod, rsop, reop, rerr, rsx, and rval are not updated on the following rising edge of rfclk. Preliminary Chapter 3: Functional Description Interface Signals © November 2009 Altera Corporation ...

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... PHY to link rsx Figure 3–16 shows the renb signal behavior. © November 2009 Altera Corporation Description Receive data valid. rval indicates the validity of the receive data signals. rval transitions low when a receive FIFO buffer is empty or at the end of a packet. When rval is high, rdat, rprty, rmod, rsop, reop, and rerr are valid ...

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... Table 3–11 describes the POS-PHY level 2 transmit interface. POS-PHY Level 2 and 3 Compiler User Guide rfclk renb (1) (2) (3) Preliminary Chapter 3: Functional Description Interface Signals (4) (5) (6) © November 2009 Altera Corporation ...

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... PHY to link stpa (3) © November 2009 Altera Corporation Description selected transmit FIFO buffer. tdat is valid only when tenb is simultaneously asserted. Data must be transmitted in big-endian order. Given the previously defined data structure, bits are transmitted in the following order: 15, 14 … … ...

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... Link to PHY Transmit FIFO buffer write clock. tfclk is used to synchronize data transfer tfclk Notes to Table 3–11: (1) The 8-bit mode is an Altera extension to the POS-PHY Level 2 specification. (2) Not present in 8-bit mode. (3) Packet-level mode only. (4) Byte-level mode only. Table 3–12 describes the POS-PHY level 2 receive interface. ...

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... For packet-level transfer, radr is also used to determine the FIFO buffers whose packet available signal is polled on the prpa output. Address 1Fh is the null-PHY address and must not be responded to by any PHY-layer device. © November 2009 Altera Corporation Description POS-PHY Level 2 and 3 Compiler User Guide Preliminary ...

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... PHY-layer device. rfclk can cycle at a any rate from 25 MHz MHz. Notes to Table 3–12: (1) The 8-bit mode is an Altera extension to the POS-PHY Level 2 specification. (2) Not present in 8-bit mode. (3) Packet-level mode only. (4) Byte-level mode only. Atlantic Interface The Atlantic interface is a full-duplex synchronous point-to-point connection protocol ...

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... End of packet. eop delineates the packet boundaries on the dat bus. When eop is high, the end of the eop packet is present on the dat bus. mty indicates the number of invalid bytes the last word is composed of when eop is asserted. eop is asserted on the last transfer of every packet. © November 2009 Altera Corporation dat par sop ...

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... A 32-bit dat bus requires a mty[1:0] signal A 64-bit dat bus requires a mty[2:0] signal mty can only be non-zero when eop is asserted. Table 3–14 shows the Atlantic control interface signal definitions. POS-PHY Level 2 and 3 Compiler User Guide Chapter 3: Functional Description Description © November 2009 Altera Corporation Preliminary Interface Signals ...

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... However, the interface is pipelined, so the delay does not affect the net throughput of the interface. Figure 3–18 on page 3–30 sink. © November 2009 Altera Corporation Description Figure 3–20). (1) shows the timing of the Atlantic interface with a master ...

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... When you include an Atlantic interface in a design, the IP Toolbench generates the signal names, which are prefixed by <port name>_, such as, b1_ena, b1_val, b2_ena, b2_val. POS-PHY Level 2 and 3 Compiler User Guide (2) (3) (4) (5) (2) (3) Preliminary Chapter 3: Functional Description Interface Signals (6) (7) (4) (5) (6) (7) © November 2009 Altera Corporation ...

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... MegaCore Verification Before releasing a version of the POS-PHY Level 2 and 3 Compiler, Altera runs a comprehensive regression test, which executes the wizard to create the instance files. Next, VHDL testbenches are run in the ModelSim simulator, to exercise the VHDL models ...

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... POS-PHY Level 2 and 3 Compiler User Guide Chapter 3: Functional Description © November 2009 Altera Corporation Preliminary MegaCore Verification ...

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... Technical training Altera literature services Non-technical support (General) (Software Licensing) Note: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions that this document uses. © November 2009 Altera Corporation Changes Made ® ...

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... A warning calls attention to a condition or possible situation that can cause you injury. The angled arrow instructs you to press the enter key. The feet direct you to more information about a particular topic. Preliminary Additional Information Typographic Conventions © November 2009 Altera Corporation ...