IPSRAMQDRII Altera, IPSRAMQDRII Datasheet

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IPSRAMQDRII

Manufacturer Part Number
IPSRAMQDRII
Description
Manufacturer
Altera
Datasheet

Specifications of IPSRAMQDRII

Lead Free Status / RoHS Status
Supplier Unconfirmed
101 Innovation Drive
San Jose, CA 95134
www.altera.com
MegaCore Function User Guide
QDRII SRAM Controller
MegaCore Version:
Document Date:
November 2009
9.1

Related parts for IPSRAMQDRII

IPSRAMQDRII Summary of contents

Page 1

... MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com QDRII SRAM Controller MegaCore Version: Document Date: 9.1 November 2009 ...

Page 2

... Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U ...

Page 3

... Control Logic .................................................................................................................................... 3–2 Resynchronization & Pipeline Logic ............................................................................................. 3–3 Datapath ............................................................................................................................................ 3–5 OpenCore Plus Time-Out Behavior .................................................................................................. 3–10 Interfaces & Signals ............................................................................................................................. 3–10 Interface Description ...................................................................................................................... 3–10 Signals .............................................................................................................................................. 3–22 Device-Level Configuration ............................................................................................................... 3–26 PLL Configuration ......................................................................................................................... 3–26 Example Design .............................................................................................................................. 3–27 Constraints ...................................................................................................................................... 3–29 Altera Corporation MegaCore Version 9.1 Contents iii ...

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... Board & Controller ......................................................................................................................... 3–31 Project Settings ................................................................................................................................ 3–33 MegaCore Verification ........................................................................................................................ 3–34 Simulation Environment ............................................................................................................... 3–34 Hardware Testing ........................................................................................................................... 3–34 Additional Information Revision History ............................................................................................................................... Info–i How to Contact Altera ..................................................................................................................... Info–i Typographic Conventions .............................................................................................................. Info–ii iv QDRII SRAM Controller MegaCore Function User Guide MegaCore Version 9.1 Altera Corporation ...

Page 5

... For more information about this release, refer to the Release Notes and Altera verifies that the current version of the Quartus compiles the previous version of each MegaCore function. The IP Library Release Notes and Errata verification. Altera does not verify compilation with MegaCore function versions older than one release ...

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... QDRII SRAM modules. The QDRII SRAM Controller ensures Description that the placement and timing are in line with QDRII specifications. The QDRII SRAM Controller is optimized for Altera Stratix series. The advanced features available in these devices allow you to interface directly to QDRII SRAM devices. ...

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... Altera clear-text resynchronization and pipeline logic and datapath with your own control logic. OpenCore Plus Evaluation With Altera’s free OpenCore Plus evaluation feature, you can perform the following actions: Altera Corporation November 2009 ...

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... QDRII SRAM 200 MHz/800 Mbps. through with the Quartus II software version 9.1. 1–4 QDRII SRAM Controller MegaCore Function User Guide Simulate the behavior of a megafunction (Altera MegaCore function or AMPP SM megafunction) within your system Verify the functionality of your design, as well as evaluate its size ...

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... Stratix GX Devices (EP1S10 to EP1S40 & EP1SGX10 to EP1SGX40 Devices) (1) Notes to (1) Table 1–6. QDRII SRAM Maximum Clock Frequency Supported in Stratix Devices (EP1S60 to EP1S80 Devices) Notes to (1) Altera Corporation November 2009 These numbers apply to both commercial and industrial devices. Frequency (MHz) DLL-Based Implementation 300 200 ...

Page 10

... QDRII SRAM Controller MegaCore Function User Guide shows typical sizes in combinational adaptive look-up tables Combinational Logic ALUTs Registers 360 598 369 633 390 708 459 880 MegaCore Version 9.1 Memory Blocks M4K M512 – – 2 – 4 – Altera Corporation November 2009 ...

Page 11

... Contains scripts that generate an instance-specific Tcl script for each instance of the QDRII SRAM Controller in various Altera devices. dat Contains a data file for each Altera device combination that is used by the Tcl script to generate the instance-specific Tcl script. doc Contains the documentation for the QDRII SRAM Controller MegaCore function. ...

Page 12

... If you obtain a license for the QDRII SRAM controller, you must set up licensing. Generate a programming file for the Altera device(s) on your board. IP Toolbench only allows you to select legal combinations of parameters, and warns you of any invalid configurations. MegaCore Version 9.1 ...

Page 13

... Constraints” on page 2–7 “Step 3: Set Up Simulation” on page 2–7 “Step 4: Generate” on page 2–8 Choose Programs > Altera > Quartus II <version> (Windows Start menu) to run the Quartus II software. Alternatively, you can use the Quartus II Web Edition software. Choose New Project Wizard (File menu). ...

Page 14

... Specify that you want to create a new custom megafunction variation and click Next. Expand the Interfaces > Memory Controllers directory then click QDRII SRAM Controller-v8.1. Select the output file type for your design; the wizard supports VHDL and Verilog HDL. MegaCore Version 9.1 Altera Corporation November 2009 ...

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... For more information on the parameters, refer to page 2. 3. Altera Corporation November 2009 The MegaWizard Plug-In Manager shows the project path that you specified in the New Project Wizard. Append a variation name for the MegaCore function output files <project path>\<variation name>. 1 The < ...

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... For more information on the project settings, refer to on page 10. Altera recommends that you turn on Automatically apply QDRII 11. Ensure Update the example design that instantiates the QDRII 12. Turn off Update example design system PLL, if you have edited the 13. The constraints script automatically detects the hierarchy of your my_system:my_system_inst|sub_system:sub_system_inst| 2– ...

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... Step 3: Set Up Simulation An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model produced by the Quartus II software. The model allows for fast functional simulation of IP using industry-standard VHDL and Verilog HDL simulators. Altera Corporation November 2009 example_top Example Design my_system_inst System ...

Page 18

... Quartus II project at the time of file generation. In most cases, the .qip file contains all of the necessary assignments and information required to process the core or system in the Quartus II compiler. Generally, a single .qip file is generated for each MegaCore function or system in the Quartus II compiler. MegaCore Version 9.1 Altera Corporation November 2009 ...

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... Altera Corporation November 2009 describes the generated files and other files that may be in your (2) & (3) Quartus II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor ...

Page 20

... After you review the generation report, click Exit to close IP Toolbench. “Simulate the Example Design” on page “Edit the PLL” on page 2–18), and compile (refer to 2–19). MegaCore Version 9.1 Description 2–11), edit the PLL(s) “Compile the Altera Corporation November 2009 ...

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... For more information on the testbench, refer to page You can use the IP functional simulation model with any Altera-supported VHDL or Verilog HDL simulator. The instructions for the ModelSim simulator are different to other simulators. Simulating With the ModelSim Simulator Altera supplies a generic memory model, lib\qdrii_model.v, which allows you to simulate the example design with the ModelSim simulator ...

Page 22

... The following variables apply in this section: <QUARTUS ROOTDIR> is the Quartus II installation directory ● <simulator name> is the name of your simulation tool ● <device name> is the Altera device family name ● <project name> is the name of your Quartus II top-level entity or ● module. <MegaCore install directory> is the QDRII SRAM Controller ● ...

Page 23

... Altera Corporation November 2009 Compile the files in Table 2–2 into the appropriate library. The files are in VHDL93 format. ...

Page 24

... Load the testbench in your simulator with the timestep set to picoseconds. Create a directory in the <project directory>\testbench directory. Launch your simulation tool inside this directory and create the following libraries.: MegaCore Version 9.1 Altera Corporation November 2009 ...

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... Table 2–4. Files to Compile—Verilog HDL IP Functional Simulation Models (Part Library altera_mf_ver <QUARTUS ROOTDIR>/eda/sim_lib/altera_mf.v lpm_ver <QUARTUS ROOTDIR>/eda/sim_lib/220model.v sgate_ver <QUARTUS ROOTDIR>/eda/sim_lib/sgate.v <device name>_ver <QUARTUS ROOTDIR>/eda/sim_lib/<device name>_atoms.v Altera Corporation November 2009 altera_mf_ver ● lpm_ver ● sgate_ver ● <device name>_ver ● ...

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... Set the Tcl variable gRTL_DELAYS to 1, which tells the testbench to model the extra delays in the system necessary for RTL simulation. Configure your simulator to use transport delays, a timestep of picoseconds and to include the auk_qdrii_lib, sgate_ver, lpm_ver, altera_mf_ver, and <device name>_ver libraries. MegaCore Version 9.1 Altera Corporation November 2009 ...

Page 27

... You can perform a simulation in a third-party simulation tool from within the Quartus II software, using NativeLink. f For more information on NativeLink, refer to the Simulating Altera IP Using NativeLink chapter in volume 3 of the Quartus II Handbook. To set up simulation in the Quartus II software using NativeLink, follow these steps: 1 ...

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... Enter the name of the automatically generated testbench, <project name>_tb, in Test bench entity. Enter the name of the top-level instance in Instance. of the memory model and the testbench, <project name>_tb, click OK and click Add. EDA RTL Simulation. 3–26. MegaCore Version 9.1 “PLL Configuration” on Altera Corporation November 2009 ...

Page 29

... When the constraints script runs, it creates another script, remove_constraints_for_<variation name>.tcl, which you can use to remove the constraints from your design. To compile the example instance, follow these steps: 1. Altera Corporation November 2009 Choose MegaWizard Plug-In Manager (Tools menu). Select Edit an existing custom megafunction variation and click Next. ...

Page 30

... Quartus II software cannot find the entity to which it is applying the constraints, probably because of a hierarchy mismatch. Either edit the constraints script, or enter the correct hierarchy path in the Hierarchy tab (refer to step page 2–6). 3–29. MegaCore Version 9.1 DTW User Guide “Constraints” on Altera Corporation November 2009 ...

Page 31

... After you obtain a license for QDRII SRAM Controller, you can request a license file from the Altera web site at install it on your computer. When you request a license file, Altera emails you a license.dat file. If you do not have Internet access, contact your local Altera representative. ...

Page 32

... Set Up Licensing 2–22 QDRII SRAM Controller MegaCore Function User Guide MegaCore Version 9.1 Altera Corporation November 2009 ...

Page 33

... Figure 3–1: (1) You can edit the qdrii_ prefix. The QDRII SRAM Controller comprises the following three parts: ■ ■ ■ Altera Corporation November 2009 3. Functional Description shows a block diagram of the QDR SRAM controller (1) QDRII SRAM Controller Resynchronization Control & Pipeline Logic ...

Page 34

... You can use the datapath on its own if you want to create you own resynchronization scheme or want to have an interface similar to the QDRII SRAM v1.0.0 interface. shows the control logic block diagram. Control Logic (Encrypted) Avalon Slave Interface Pause Avalon Slave Interface MegaCore Version 9.1 Write FSM Read FSM Altera Corporation November 2009 ...

Page 35

... Read Data Read FSM Pipeline Address & Command Pipeline The optional address and command pipeline pipelines all commands and addresses by a predefined number of cycles. Altera Corporation November 2009 shows the resynchronization and pipeline logic block Resynchronization & Pipeline Logic Training Group ...

Page 36

... It takes a certain amount of time to propagate the first data to the memory and read it back. This first set of clock cycles is deemed invalid and is not taken into account. 3–4 QDRII SRAM Controller MegaCore Function User Guide MegaCore Version 9.1 Altera Corporation November 2009 ...

Page 37

... The RAM size ensures there is minimal latency, but there is enough slack to compensate for the training pattern realignment. Datapath Figure 3–4 on page 3–6 Altera Corporation November 2009 shows the datapath block diagram. MegaCore Version 9.1 QDRII SRAM Controller MegaCore Function User Guide Functional Description 3– ...

Page 38

... Output Registers Address & Command Output Registers From Write FSM Capture Registers Capture Registers MegaCore Version 9.1 Datapath Clock Generator Address & Command Output Registers Write Registers Write Registers Capture Group Modules Read CQ/CQN Group Read CQ/CQN Group Altera Corporation November 2009 ...

Page 39

... The controller uses the 90shifted cq and cqn clocks for the capture registers of the q bus. When captured, the controller synchronizes the two words on a double width bus. Altera Corporation November 2009 Address Read Write Write byte enable CQ/CQN group module Read capture registers MegaCore Version 9 ...

Page 40

... For a device depth of two, it shares the q and cq/cqn signals. All the signals go out of the block with their associated internal cq clock, so you can use Altera's resynchronization scheme or implement your own. Altera recommends the following read capture implementation for data captures from QDRII SRAM devices when using complementary echo clocks (cq and cqn signals) ...

Page 41

... The output of latch B is either real B or expected B, depending on the relationship between cq and cqn. To cover both cases, the usable part of B signal should be captured before going to the resynchronization FIFO buffers. Routing delay aligns the data with the clock. Altera Corporation November 2009 I/O Fabric ...

Page 42

... For MegaCore functions, the untethered time out is 1 hour; the tethered time out value is indefinite. Megafunctions. “Interface Description” on page 3–10 “Signals” on page 3–22 MegaCore Version 9 and AN 320: OpenCore Plus Altera Corporation November 2009 ...

Page 43

... Altera Corporation November 2009 Writes Reads Simultaneous Read & Write Timing Specifications. “Isolated Write” on page 3–11 “Bursts” on page 3–13 “Bursts with Pauses” on page 3–14 “Bursts” on page 3–13). Non-consecutive addresses are split 3– ...

Page 44

... QDRII SRAM Controller MegaCore Function User Guide shows a burst of two, the controller takes the data straight 0001 0001 shows a burst of four (wide mode), all the data is MegaCore Version 9.1 0001 0002 0002 0001 0001 00 00 Altera Corporation November 2009 ...

Page 45

... Avalon interface at consecutive addresses, the controller automatically concatenates them and transfers them to the QDRII SRAM, if the first one is an even address. If more data is coming in the following cycle also sent straight away, without any pause. Altera Corporation November 2009 01020304 01020304 0001 0001 shows the burst of four (narrow mode) ...

Page 46

... A one-cycle write to address <a> followed straight away by a two- cycle transfer to addresses <b> and <b + 1> The second half of the transfer to <b> is paused for a clock cycle MegaCore Version 9.1 0001 0002 0003 0004 0004 0002 00 00 Figure 3–7 on page 3–11. Altera Corporation November 2009 ...

Page 47

... The controller captures and resynchronizes the data onto the system clock and it appears on the Avalon interface a few cycles later. The controller asserts avl_data_read_valid with the data to validate the data cycle. Altera Corporation November 2009 11051106 11051106 ...

Page 48

... QDRII SRAM Controller MegaCore Function User Guide 0001 0001 shows a single read request from the Avalon interface for a 0001 0001 MegaCore Version 9.1 0102 0102 xx xx 0102 0102 Altera Corporation November 2009 ...

Page 49

... Avalon read. The burst consists of two consecutive read requests. The controller sends one read request to the memory, which returns the four half cycles of value. After resynchronization, the data is sent back to the Avalon interface. Altera Corporation November 2009 shows the behavior of a single read request for a burst of four 0001 0001 3– ...

Page 50

... The following two reads still get concatenated to make a burst of four, avoiding loss of bandwidth. 3–18 QDRII SRAM Controller MegaCore Function User Guide 0003 0002 Figure 3–16 on page 3–19 MegaCore Version 9.1 0102 0304 0304 04 shows a read Altera Corporation November 2009 ...

Page 51

... When a read and a write arrive at the same time, the write takes priority over the read. For a continuous read and write, there is a one off pause on the read side, refer to Altera Corporation November 2009 0001 1220 “ ...

Page 52

... QDRII SRAM Controller MegaCore Function User Guide 1002 1003 1718 3000 1000 3002 1002 Figure 3–18 on page 3–21 shows concurrent reads and writes in a MegaCore Version 9.1 0102 0304 0506 0708 18 08 Altera Corporation November 2009 0708 ...

Page 53

... Similarly to the two cycles, you must alternate the read and write commands on the QDRII SRAM interface result, there is a pause when both the read and write commands arrive simultaneously on the Avalon interfaces. The first read is buffered and then the consecutive read is delayed by one clock cycle, refer to Altera Corporation November 2009 ...

Page 54

... Description System clock derived from the PLL. Write clock derived from the PLL. Reset signal, which you can assert asynchronously, but you must deassert synchronously to avl_clk Delay bus for DLL to shift DQS inputs. DQS mode only. Altera Corporation November 2009 . ...

Page 55

... Width (Bits) Direction  21 avl_addr_rd avl_byteen_rd 1 avl_chipselect_rd 1 avl_read 18, 36, 72, avl_data_rd 144, or 288 Altera Corporation November 2009 Signal Direction Input Non-DQS capture mode clock. Output Asserted when the training of the core is complete. Output The core is nonfunctional. Asserted when the training reaches the maximum number of iterations but fails to adjust the pointers ...

Page 56

... Free running clock from memory. Data out. Free running clock to memory. Free running clock to memory. Data in from memory. Read signal to memory. Active low and reset in the inactive state. Write signal to memory. Active low and reset in the inactive state. Description Altera Corporation November 2009 ...

Page 57

... Altera Corporation November 2009 Direction Input Write signal from the pipeline and resynchronization logic. Input DLL delay control from the top-level design to shift the nominal 90 degrees. Output Capture clocks (CQ into soft logic) to the pipeline and resynchronization logic ...

Page 58

... Stratix series is to use a single enhanced PLL to produce all the required clock signals. No external clock buffer is required as the Altera device can generate clock signals for the QDRII SRAM devices. For Stratix II devices, if you turn off DQS mode, you enable fed-back resynchronization, which uses a fed-back clock to resynchronize the data. Figure 3– ...

Page 59

... PLL and all the logic. When the PLL is locked and avl_resetn is deasserted, the reset to the core, soft_reset_n, is also deasserted. If the PLL lock is lost, the reset logic issues a reset. Figure 3–21 on page 3–28 Altera Corporation November 2009 Stratix II DLL (Note 1) ...

Page 60

... Megawizard. MegaCore Version 9.1 QDRII SRAM Model DLL Description Testbench for the example design. Example design. Example PLL, which you should configure to match your frequency. Example driver. QDRII SRAM controller. Altera Corporation November 2009 ...

Page 61

... The testbench instantiates a QDRII SRAM model, a reference clock for the PLL, and model for the system board memory trace delays. Altera provides a Verilog HDL simulation model. The model is a behavioral model to verify the design but does not simulate any delays. Altera recommends that you replace the model with the specific model from your memory vendor ...

Page 62

... For QDRII, 1.5; for QDRII+, 2.0 or 2.5 Table 3–8: IP Toolbench allows you to enter up to 600 MHz, but Altera only supports the QDRII SRAM controller up to 300 MHz. MegaCore Version 9.1 Description A part number for a particular memory device. Choosing an entry other than Custom sets many of the parameters in the wizard to the correct value for the specified part ...

Page 63

... Value Number of pipeline registers on address, command, and data outputs Number of pipeline registers on read data Altera Corporation November 2009 shows the local bus width parameter (only available with burst Parameter Value Narrow mode or wide mode shows the memory interface parameters. Parameter Value ...

Page 64

... MegaCore Version 9.1 Description Turn on if you want to choose the latency clock cycle. Choose the latency clock cycle. For example, if the default is 13, you can choose any value from 11 to 17. However, Altera recommends that you do not alter this parameter. Altera Corporation November 2009 ...

Page 65

... Table 3–17. Pin Prefixes Parameter Prefix all QDRII SRAM This string prefixes the pin names for the FPGA pins that are connected to the QDRII pins with SRAM controller. Altera Corporation November 2009 shows the example settings. Description shows the variation path parameters. Description shows the pin prefixes parameter ...

Page 66

... Verification Simulation Environment Altera has carried out extensive tests using industry-standard models to ensure the functionality of the QDRII SRAM controller. In addition, Altera has carried out a wide variety of gate-level tests of the QDRII SRAM controller to verify the post-compilation functionality of the controller. Hardware Testing Table 3–18 hardware tested the QDRII SRAM controller. Table 3– ...

Page 67

... Additional Information Changes Made wpsn and rpsn Contact Contact (1) Method Website Website Email Website Email (Software Licensing) Email You can also contact your local Altera sales office or sales representative. MegaCore Version 9.18.0 signals. Address www.altera.com/support www.altera.com/training custrain@altera.com www.altera.com/literature nacomp@altera.com authorization@altera.com Info–i ...

Page 68

... The feet direct you to more information about a particular topic. Info–ii QDRII SRAM Controller MegaCore Function User Guide Meaning , , and Active-low signals are denoted by suffix tdi input. . resetn c:\qdesigns\tutorial\chiptrip.gdf ). TRI MegaCore Version 9.1 . For and logic function SUBDESIGN Altera Corporation November 2009 ...

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