EPXA4F1020C1 Altera, EPXA4F1020C1 Datasheet

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EPXA4F1020C1

Manufacturer Part Number
EPXA4F1020C1
Description
Manufacturer
Altera
Datasheet

Specifications of EPXA4F1020C1

Device System Gates
1052000
Function
Excalibur Device
Frequency (max)
200MHz
Operating Supply Voltage (typ)
1.8V
Mounting
Surface Mount
Pin Count
1020
Package Type
FCFBGA
Lead Free Status / RoHS Status
Not Compliant

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DS-EXCARM-2.0
Features...
Altera Corporation
May 2002, ver. 2.0
I
I
I
I
I
I
I
I
I
Combination of a world-class RISC processor system with industry-
leading programmable logic on a single device
Industry-standard ARM922T
at up to 200 MHz
APEX
100,000 to 1,000,000 gates (see
Advanced bus architecture based on advanced microcontroller bus
architecture (AMBA
Embedded programmable on-chip peripherals
Advanced memory support
PLD configuration/reconfiguration possible via the embedded
processor software
Fully configurable memory map
Extensive embedded system debug facilities
ARMv4T instruction set with Thumb
Memory management unit (MMU) included for real-time
operating system (RTOS) support
Harvard cache architecture with 64-way set associative separate
8-Kbyte instruction and 8-Kbyte data caches
ETM9 embedded trace module to assist software debugging
Flexible interrupt controller
Universal asynchronous receiver/transmitter (UART)
General-purpose timer
Watchdog timer
Internal single-port SRAM up to 256 Kbytes
Internal dual-port SRAM up to 128 Kbytes
Internal SDRAM controller
-
-
-
Expansion bus interface (EBI)
-
-
SignalTap
ARM
Real-time data/instruction processor trace
Background debug monitoring via the IEEE Std. 1149.1 (JTAG)
interface
20KE-like programmable logic architecture ranging from
Single data-rate (SDR) and double data-rate (DDR) support
Up to 512 Mbytes
Data rates to 133 (266) MHz
Compatible with industry-standard flash memory, SRAMs,
and peripheral devices
Four devices, each up to 32 Mbytes
®
JTAG processor debug support
embedded logic analyzer
Excalibur Device Overview
) high-performance bus (AHB)
Table 1
32-bit RISC processor core operating
on
page
®
extensions
3)
Data Sheet
1

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EPXA4F1020C1 Summary of contents

Page 1

... May 2002, ver. 2.0 I Features... Altera Corporation DS-EXCARM-2.0 Excalibur Device Overview Combination of a world-class RISC processor system with industry- leading programmable logic on a single device ™ Industry-standard ARM922T 200 MHz – ARMv4T instruction set with Thumb – Memory management unit (MMU) included for real-time operating system (RTOS) support – ...

Page 2

... PLD, bus connections, and peripherals – C/C++ compiler, source-level debugger, and RTOS support This document provides updated information about Excalibur devices and should be used together with the APEX 20K Programmable Logic Device Family Data Sheet. Tables 2 and 3 on page 3) ™ Altera Corporation ...

Page 3

... Maximum user I/Os UART, timer, watchdog timer JTAG debug module Embedded trace module General purpose I/O Port Low-power PLL Note: (1) Maximum available user I/Os = shared stripe I/O + PLD I/O Altera Corporation EPXA1 ARM922T 200 MHz 32 Kbytes 16 Kbytes 100,000 4,160 26 263,000 246 ...

Page 4

... PLD to be independently optimized for maximum performance. Trace SRAM Module DPRAM ARM922T 32 Kbytes SRAM 16 Kbytes DPRAM 128 Kbytes SRAM 64 Kbytes DPRAM SRAM SRAM Embedded Processor Stripe DPRAM DPRAM PLD 256 Kbytes SRAM 128 Kbytes DPRAM Altera Corporation ...

Page 5

... Bridge AHB Port A Slave Port PLD PLD Master(s) Master(s) User Modules Requiring Direct Access to Large Dual-Port or Single-Port RAMs PLD PLD Clock Domain(s) AHB2 Clock Domain Altera Corporation SDRAM Interrupt Watchdog SDRAM Controller Timer Controller Configu- ration Logic Master Single- PLL Port ...

Page 6

... AHB-to-AHB bridges enable embedded peripherals and PLD-implemented peripherals to exchange data with the embedded processor or with other peripherals. The Excalibur family is supported by the following development tools: I SOPC Builder from Altera I Quartus II from Altera I ADS, GNUPro and other third-party tools The Excalibur system architecture (embedded processor bus ...

Page 7

... Figure 3. ARM922T Embedded Processor Internal Organization Instruction MMU C13 IVA(31..0) ARM9TDMI JTAG Processor Core (+ Embedded ICE Interface) DVA(31..0) C13 Data MMU C13 Context Identification Register Altera Corporation IPA(31..0) Instruction Embedded Cache Trace (8 Kbyte) Module IMVA(31..0) ID(31..0) DD(31..0) DMVA(31..0) Write-Back Page Data Cache ...

Page 8

... I Additional embedded processor interrupt sources and controls PLD designers can take full advantage of the extensive range of Altera intellectual property (IP) Megacore complex system-on-a-programmable-chip (SOPC) designs in minimal time but with maximum customization. The bidirectional bridges and dual-port memory interfaces between the embedded stripe and the PLD are synchronous to the clock domain that drives them ...

Page 9

... Altera Corporation In addition, there are either one or two blocks of dual-port SRAM in the embedded stripe, depending on the device type. The outputs of the dual-port memories can be registered. One of the ports gives dedicated access to the PLD; the other port can be configured for access by AHB masters or by the PLD. The width of the data port to the PLD is configurable as × ...

Page 10

... PLD design process, Altera provides seamless support with SOPC Builder and Quartus II; ADS, GNUPro and third-party development tools are also available. See the Altera web site, http://www.altera.com, for details of the software development tools. Excalibur devices are compatible with any available tools for the ARM922T from ARM or third parties ...

Page 11

... Figure 4. Sample SOPC Builder Screen Altera Corporation Quartus II The Quartus II development system can be used for both PLD logic design and the integration of embedded software. The Quartus II software provides an integrated package for complete hardware logic design, including HDL and schematic design entry, ...

Page 12

... Figure 5. Quartus II Development Tool Flow Hardware Design Entry Synthesis Place and Route PLD Configuration Image Configuration Device ™ co-design capability, embedded SOPC Builder Excalibur Software MegaWizard Design Entry Assemble, Compile and Link Software Executable Image Image Conversion Flash Serial Image Bitstream Altera Corporation ...

Page 13

... Configuration Altera Corporation Altera supplies a variety of embedded software functions to support flash memory programming and PLD configuration. Excalibur devices are configured at system power-up with data stored in a configuration device or flash memory. The same memory can store application software for the embedded processor. The user can reconfigure the device in-circuit by using the on-chip processor, using configuration data stored anywhere in its memory system ...

Page 14

... Clk_ref 6 4-Mbyte Flash Memory PHY Transceiver 8 Daughter Card Connector 9 PCI Connectors 10 Mictor Connector (EBI) 11 Mictor Connector (JTAG) 12 Mictor Connector (SDRAM Mictor Connector (ETM9) 14 SDRAM DIMM Module 15 Mictor Connector (UART + EBI) 16 Power Supply ATX Connector PSU 18 MasterBlaster Connector 19 Multi-ICE Connector 19 Altera Corporation ...

Page 15

... Ethernet PHY MAC Customer Implementation ARM-Based Embedded Processor Stripe Altera IP Implementation Non-PLD Solution Altera Corporation The EPXA10 development kit provides a powerful platform for designing embedded processor PLD solutions. The kit features the EPXA10 device, a member of the Excalibur family with an ARM922T-based processor subsystem tightly coupled to the PLD fabric ...

Page 16

... Revision History Copyright © 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as 101 Innovation Drive trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U ...

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