IDT7210L20J IDT, Integrated Device Technology Inc, IDT7210L20J Datasheet - Page 4

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IDT7210L20J

Manufacturer Part Number
IDT7210L20J
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheets

Specifications of IDT7210L20J

Package Type
LCC
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Supplier Unconfirmed

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IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
PRELOAD TRUTH TABLE
NOTES:
ABSOLUTE MAXIMUM RATINGS
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
Hi Z = Output buffers at high impedance (output disabled)
Symbol
V
V
T
T
T
I
PREL
PL = Output buffers at high impedance or output disabled. Preload data
OUT
A
BIAS
STG
Q = Output buffers at low impedance. Contents of output register will be
CC
TERM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
transferred to output pins.
supplied externally at output pins will be loaded into the output
register at the rising edge of CLKP.
Power Supply
Voltage
Terminal Voltage
with Respect to
GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
TSX
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Rating
TSM
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TSL
Commercial
–55 to +125
–55 to +125
-0.5 to +7.0
V
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 to +70
CC
–0.5 to
50
+0.5V
XTP
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
PL
PL
PL
PL
Q
Q
Q
Q
(1)
–55 to +125
–65 to +135
–65 to +150
-0.5 to +7.0
V
Military
CC
–0.5 to
MSP
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
PL
PL
PL
PL
Q
Q
Q
Q
50
+0.5V
2577 tbl 02
2577 tbl 03
LSP
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
PL
PL
PL
PL
Q
Q
Q
Q
Unit
mA
V
V
C
C
C
11.2
CAPACITANCE
NOTE:
1. This parameter is measured at characterization and not 100%tested.
NOTES ON TWO'S COMPLEMENT FORMATS
1. In two's complement notation, the location of the binary
2. When in the non-accumulating mode, the first four bits (P
3. In operations that require the accumulation of single prod-
Symbol
C
C
IN
OUT
point that signifies the separation of the fractional and
integer fileds is just after the sign, between the sign bit
This same format is carried over to the output format,
except that the extended significance of the integer filed is
provided to extend the utility of the accumulator. In the
case of the output rotation, the output binary point is
located between the2 and 2
the binary point is arbitrary, as long as there is consistency
with both the input and output formats. The number filed
can be considered entirely integer with the binary point just
to the right of the least significant bit for the input, product
and the accumulated sum.
to P
the P
when multiplying -1 x -1. With the additional bits that are
available in this multiplier, the –1 x –1 is a valid operation
that yields a +1 product.
ucts or sum of products, there is no change in format. To
allow for a valid summation beyond that available for a
single multiplication product, three additional significant
bits (guard bits) are provided. This is the same as if the
product was accumulated off-chip in a separate 35-bit wide
adder. Taking the sign at the most significant bit position
will guarantee that the largest number field will be used.
When the accumulated sum only occupies the right hand
portion of the accumulator, the sign will be extended into
the lesser significant bit positions.
(-2 ) and the next significant bit for the multiplier inputs.
31
) will all indicate the sign of the product. Additionally,
30
term will also indicate the sign with one exception,
Input Capacitance
Output Capacitance
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Parameter
(T
A
= +25 C, f = 1.0MHz)
(1)
1
bit positions. The location of
Conditions
V
V
OUT
IN
= 0V
= 0V
Max. Unit
10
12
2577 tbl 04
pF
pF
4
34

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