74F283SC Fairchild Semiconductor, 74F283SC Datasheet - Page 2

• Manufacturer Part Number: 74F283SC
• Manufacturer: Fairchild Semiconductor

Specifications of 74F283SC

• Logic Family: F
• Logical Function: Binary Full Adder
• Technology: Bipolar
• Number Of Elements: 1
• Number Of Bits: 4
• Propagation Delay Time: 13ns
• High Level Output Current: -1mA
• Low Level Output Current: 20mA
• Package Type: SOIC N
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Pin Count: 16
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

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Functional Description
The 74F283 adds two 4-bit binary words (A plus B) plus the
incoming Carry (C
(S
of the various inputs and outputs is indicated by the sub-
script numbers, representing powers of two.
Interchanging inputs of equal weight does not affect the
operation. Thus C
pins 5, 6 and 7 for DIPS, and 7, 8 and 9 for chip carrier
packages. Due to the symmetry of the binary add function,
the 74F283 can be used either with all inputs and outputs
active HIGH (positive logic) or with all inputs and outputs
active LOW (negative logic). See Figure 1. Note that if C
not used it must be tied LOW for active HIGH logic or tied
HIGH for active LOW logic.
Due to pin limitations, the intermediate carries of the
74F283 are not brought out for use as inputs or outputs.
Active HIGH: 0
0
–S
3
) and outgoing carry (C
Logic Levels
Active HIGH
Active LOW
2
10
0
FIGURE 4. 5-Input Encoder
S
(A
2
0
9
FIGURE 2. 3-Bit Adder
0
2
0
0
). The binary sum appears on the Sum
, A
(A
3
2S
Where ( )
B
2
0
16
1
, B
0
B
0
4S
C
2
)
can be arbitrarily assigned to
0
Active LOW: 1
C
4
)
2
L
0
1
FIGURE 1. Active HIGH versus Active LOW Interpretation
) outputs. The binary weight
0
2
3
2
8S
plus
1
(A
A
(A
3
L
0
1
3
0
1
16C
B
3
B
A
H
5
1
0
)
1
1
4
)
6
A
12
L
0
1
2
0
A
H
1
0
0
3
is
B
H
1
0
2
0
However, other means can be used to effectively insert a
carry into, or bring a carry out from, an intermediate stage.
Figure 2 shows how to make a 3-bit adder. Tying the oper-
and inputs of the fourth adder (A
dependent only on, and equal to, the carry from the third
adder. Using somewhat the same principle, Figure 3 shows
a way of dividing the 74F283 into a 2-bit and a 1-bit adder.
The third stage adder (A
means of getting a carry (C
(via A
stage on S
whether HIGH or LOW, they do not influence S
when A
does not influence the carry out of the third stage. Figure 4
shows a method of implementing a 5-input encoder, where
the inputs are equally weighted. The outputs S
present a binary number equal to the number of inputs I
I
ing a 5-input majority gate. When three or more of the
inputs I
5
that are true. Figure 5 shows one method of implement-
B
L
0
1
1
2
1
and B
2
–I
and B
B
L
0
1
5
2
2
are true, the output M
FIGURE 3. 2-Bit and 1-Bit Adders
. Note that as long as A
FIGURE 5. 5-Input Majority Gate
2
) and bringing out the carry from the second
2
B
H
1
0
are the same the carry into the third stage
3
S
H
1
0
0
2
, B
S
10
H
1
0
1
) signal into the fourth stage
2
, S
5
S
L
0
1
2
is true.
3
2
) is used merely as a
2
, B
and B
3
S
) LOW makes S
L
0
1
3
2
are the same,
C
0
H
1
0
2
, S
4
. Similarly,
1
and S
1
–
3
2