SSTE32882KA1AKG IDT, Integrated Device Technology Inc, SSTE32882KA1AKG Datasheet

SSTE32882KA1AKG

Manufacturer Part Number

SSTE32882KA1AKG

Description

Manufacturer

IDT, Integrated Device Technology Inc

Datasheet

1.SSTE32882KA1AKG.pdf (75 pages)

Specifications of SSTE32882KA1AKG

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1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY

TEST AND QUAD CHIP SELECT

Description

This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock

driver with parity is designed for 1.25V, 1.35V and 1.5V V

operation.

All inputs are 1.25,1.35V and 1.5V CMOS compatible, except the

reset (RESET) and MIRROR inputs which are LVCMOS. All

outputs are 1.25V,1.35V and 1.5V CMOS edge-controlled drivers

optimized to drive single terminated 25Ω to 50Ω traces in DDR3

RDIMM applications, except the open-drain error (ERROUT)

output. The clock outputs (Yn and Yn) and control net outputs

QnCKEn, QnCSn and QnODTn are designed with a different

strength and skew to compensate for different loading and

equalize signal travel speed.

The SSTE32882KA1 has two basic modes of operation

associated with the Quad Chip Select Enable (QCSEN) input.

When the QCSEN input pin is open (or pulled high), the

component has two chip select inputs, DCS0 and DCS1, and two

copies of each chip select output, QACS0, QACS1, QBCS0 and

QBCS1. This is the "QuadCS disabled" mode. When the

QCSEN input pin is pulled low, the component has four chip

select inputs DCS[3:0], and four chip select outputs, QCS[3:0].

This is the "QuadCS enabled" mode. Through the remainder of

this specification, DCS[n:0] will indicate all of the chip select

inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS

enabled. QxCS[n:0] will indicate all of the chip select outputs.

The SSTE32882KA1 includes a high-performance, low-jitter,

low-skew buffer that distributes a differential clock input (CK

and CK) to four differential pairs of clock outputs (Yn and Yn),

and to one differential pair of feedback clock outputs (FBOUT

and FBOUT). The clock outputs are controlled by the input

clocks (CK and CK), the feedback clocks (FBIN and FBIN), and

the analog power inputs (AV

grounded, the PLL is turned off and bypassed for test purposes.

The SSTE32882KA1 operates from a differential clock (CK and

CK). Data are registered at the crossing of CK going high, and

CK going low. The data is either driven to the corresponding

device outputs if exactly one of the DCS[n:0] input signals is

driven low.

Based on the control register settings, the device can change its

output characterisitics to match different DIMM net topologies.

The timing can be changed to compensate for different flight time

of signals within the target application. By disabling unused

outputs the power consumption is reduced.

The SSTE32882KA1 accepts a parity bit from the memory

controller on the parity (PAR_IN) input, compares it with the data

received on the DIMM-independent data inputs (DAn, DBAn,

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT

THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE

and AV

). When AV

DRAS, DCAS, and DWE), and indicates whether a parity error

has occurred on the open-drain ERROUT pin (active low). The

convention is even parity; i.e., valid parity is defined as an even

number of ones across the DIMM-independent data inputs

combined with the parity input bit. To calculate parity, all

DIMM-independent D-inputs must be tied to a known logic state.

The DIMM-dependent signals (DCKEn, DODTn, and DCSn) are

not included in the parity check computation.

To ensure defined outputs from the register before a stable clock

has been supplied, RESET must be held in the low state during

power-up.

The SSTE32882KA1 is available in a 176-ball BGA with

0.65mm ball pitch in a 11 x 20 grid. The device pinout supports

outputs on the outer two left and right columns to support easy

DIMM signal routing. Corresponding inputs are placed in a-way

that two devices can be placed back-to-back for four Rank

modules while the data inputs share the same vias. Each input and

output is located close to an associated no ball position or on the

outer two rows to allow low cost via technology combined with

the small 0.65mm ball pitch.

SSTE32882KA1

Advanced Information

SSTE32882KA1

DATASHEET

7314/8

Related parts for SSTE32882KA1AKG

SSTE32882KA1AKG Summary of contents

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REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V V operation. All inputs are 1.25,1.35V and ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Features • Pinout optimizes DDR3 RDIMM PCB layout • DDR3-800/1066/1333/1600/1866/2133 rate • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs • Phase Lock Loop ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Block Diagram - Register and PLL Logic Diagram (Positive Logic) V REF DA3..DA9, DA11, DA13..DA15, DBA0..DBA2 DA0-DA2, DA10, DA12, DRAS, DCAS, DWE (1) DCS[n:0] DCKE0, DCKE1 DODT0, DODT1 ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Block Diagram - Parity Logic Diagram (Positive Logic) V REF DA0..DA15, DBA0..DBA2, DRAS, DCAS, DWE PAR_IN DCS[n:0] DCKE0, DCKE1 DODT0, DODT1 RESET CK CK FBIN FBIN 1 DCS[n:0] ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Pinout Configuration Package options include a 176-ball Thin-Profile Fine-Pitch BGA (TFBGA) with 0.65mm ball pitch grid, 8.0mm x 13.5mm. It uses the mechanical outline MO-246 ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Pin Descriptions The device has symmetric pinout with the inputs on the south side and the outputs on the east and west sides. This allows back-to-back mounting on ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Ball Assignment: MIRROR = HIGH, QCSEN = HIGH or float This table specifies the pinout for the SSTE32882KA1 in the back configuration (QuadCS mode disabled). Balls A9 and ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Ball Assignment: MIRROR = LOW, QCSEN = LOW This table specifies the pinout for the SSTE32882KA1 in the front configuration (QuadCS mode enabled). Balls A9 and W7 are ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Ball Assignment: MIRROR = HIGH, QCSEN = LOW This table specifies the pinout for the SSTE32882KA1 in the back configuration (QuadCS mode enabled). Balls A9 and W7 are ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Terminal Functions Signal Group Signal Name Ungated inputs DCKEn, DODTn Chip Select DAn, DBAn, DRAS, gated inputs DCAS, DWE Chip Select DCS0, DCS1 inputs DCS2, DCS3 Re-driven QxAn, ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Signal Group Signal Name 1 Power Vrefca Vdd Vss AVdd AVss PVdd PVss RSVD 1 1.25V/1.35V/1.5V CMOS inputs use V 2 These outputs are optimized for memory applications ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Function Table (Each Flip Flop) with QuadCS Mode Enabled Inputs RESET DCS[3:0] H LLHH H HHLL H LLLL H XXXX H LHHH H HLHH H HHLH H HHHL ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Parity, Low Power and Standby with QuadCS Mode Disabled RESET DCS0 ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Parity, Low Power and Standby with QuadCS Mode Enabled RESET DCS[3:0] H LXXX XLXX XXLX XXXL H LXXX XLXX XXLX XXXL H LXXX XLXX XXLX XXXL H LXXX ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT PLL Function Table Inputs RESET VDD nominal H VDD nominal H VDD nominal H VDD nominal H VDD nominal 3 H GND 3 ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Absolute Maximum Ratings Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT DC Specifications - Voltage The SSTE32882KA1 parametric values are specified for the device default control word settings, unless otherwise stated. Note that the RC10 setting does not affect ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Symbol Parameter V Differential Output Crosspoint Voltage (1.5V Operation) OX Differential Output Crosspoint Voltage (1.35V Operation) 1 DCKE0/1, DODT0/1, DA0..DA15, DBA0..DBA2, DRAS, DCAS, DWE, PAR_IN, DCS[1:0] when QCSEN ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT DC Specifications - Voltage (DDR3U 1.25V) Symbol Parameter V DC Supply voltage (1.25V Operation Reference voltage REF V DC Termination voltage HIGH-level ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Thermal Symbol Parameter T 1 Case temperature case (max) 1 Measurement procedure JESD51-2 2 This spec is meant to guarantee 125C by the SSTE32882KA1 device. ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Capacitance Values Symbol Parameter Input capacitance, Data inputs C I Input capacitance, CK, CK, FBIN, FBIN‘ Output capacitance, Re-driven and Clock C Outputs O C Delta capacitance over ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Timing Requirements Symbol Parameter Input Clock Frequency f CLOCK Input Clock Frequency f TEST Pulse Duration, CK HIGH or LOW Inputs active time ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 5 Setup (t ) nominal slew rate for a rising signal is defined as the slew rate between the last crossing first crossing of V ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Timing Requirements (DDR3U 1.25V) Symbol Parameter Input Clock Frequency f CLOCK Input Clock Frequency f TEST Pulse Duration, CK HIGH or LOW Inputs ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Voltage Waveforms for Setup and Hold Times–Hold Time Calculation DDQ MIN MIN ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Voltage Waveforms for Setup and Hold Times–Setup Time Calculation DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V max IL(ac) V ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT AC Specifications - Output Timing Requirements 1 Symbol Parameter Propagation delay, single-bit switching (1.5V operation) t PDM Propagation delay, single-bit switching 3 (1.35V operation) Output disable time (1/2-Clock ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT AC Specifications - Output Timing Requirements Symbol Parameter Propagation delay, single-bit t PDM switching (1.25V operation) Output disable time (1/2-Clock pre-launch) t DIS Output enable time (1/2-Clock pre-launch) ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Output Buffer Characteristics - edge rates over specified operating free-air temperature range Symbol Parameter 1 rising edge slew rate (1.5V operation) dV/dt_r 1 rising edge slew rate (1.35V ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Clock Driver Characteristics at Application Frequency (frequency band 1) Symbol Parameter Cycle-to-cycle period JIT CC jitter Cycle-to-cycle period JIT CC jitter t ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Symbol Parameter Maximum variation in 6 delay between the input t DYNOFF & output clock SSC modulation frequency SSC clock input frequency deviation t PLL Loop bandwidth BAND ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 4. This skew represents the absolute Qn skew compared to the output clock (Yn), and contains the register pad skew, clock skew and package routing skew (See “Qn ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Yn Yn Qn(C/A) Ideal Qn(C/A) Late Qn(C/A) Early Yn Yn Qn(C/A) Ideal Qn(C/A) Late Qn(C/A) Early 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT THE ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Clock Driver Characteristics at Test Frequency (frequency band 2) Symbol Cycle-to-cycle period jitter JIT CC t Stabilization time STAB Total Clock Output skew t CKSK ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Initialization The SSTE32882KA1 can be powered-on at 1.5V, 1.35V or 1.25V. After the voltage transition, stable power is provided for a minimum of 200 µs with RESET asserted. ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT From a device perspective, the initialization sequence must be as shown in the following Device Initialization table. SSTE32882KA1 Device Initialization Sequence Step Power VDD, AVDD, RESET Vref PVDD ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Timing of clock and data during initialization sequence with stable power Step 0,1 Step 2 ( RESET DCKE[0: (2) DA/C DODT[0:1] H ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT SSTE32882KA1 Device Initialization Sequence Step Power Inputs: Signals provided by the controller VDD, RESET Vref DCS AVDD, [n:1] PVDD stable voltage stable V 1 ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Input ( PAR_IN ERROUT 1 CK left out for better visibility. The next figure shows the parity diagram with two consecutive parity-error occurrences and assumes the ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Two Parity-Error Occurrences Separated by two Clock Cycles of no Error Occurrence n Input ( CA0 PAR_IN ERROUT 1 CK left out for better visibility. The ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT n Input (1) CK CA0 CA PAR_IN DCS0 DCS1 ERROUT 1 CK left out for better visibility. POWER SAVING MODES The device supports different power saving mechanisms. When ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT REGISTER CKE POWER DOWN WITH IBT OFF Upon entry into CKE Power Down mode with IBT off, all register input buffers including IBT are disabled except for CK/CK, ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT To re-enable the register from this power saving state, valid logic levels are required at all register inputs when either or both DCKEn inputs are driven high. Upon ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT n-1 n n+4 CK RESET DAn,DBAn Hi-Z DRAS Hi-Z DCAS, DWE PAR_IN Hi-Z DODTn tInDIS DCKEn ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT CLOCK STOPPED POWER DOWN MODE To support S3 Power Management mode or any other operation that allows Yn clocks to float, the SSTE32882KA1 supports a Clock Stopped power ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Input n-1 n CK/CK High RESET Hi-Z DAn, DBAn DRAS Hi-Z DCAS DWE Hi-Z PAR_IN High, Low or Toggling ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Input n-1 n CK/CK High RESET DAn, DBAn DRAS DCAS DWE PAR_IN High or Low DODTn tInDIS DCKEn High High or Low DCS[i,0] High High ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT DYNAMIC 1T/3T TIMING TRANSACTION AND OUTPUT INVERSION ENABLING/DISABLING Output Inversion is always enabled by default, after RESET is de-asserted, to conserve power and reduce simultaneous output switching current. ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT n n+1 Input (1) CK DCKE[1:0] DA[15:0], DBA[2:0] DODT[1:0] DRAS DCAS, DWE DCS0 (2) DCS[n:1] Outputs n n (1) Yn QCKE[1:0] QAA[15:0], QABA[2:0], QBA12, QBA10, QBA[2:0] ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT CONTROL WORDS The SSTE32882KA1 registers have internal control bits for adapting the configuration of certain device features. The control bits are accessed by the simultaneous assertion of both ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Control Words The device features a set of control words, which allow the optimization of the device properties for different raw card designs. The different control words and ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Control Word Decoding with QuadCS Mode Disabled Control Word Symbol DCS0 None n/a H None n/a X Control word 0 RC0 L Control word 1 RC1 L Control ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Control Word Decoding with QuadCS Mode Enabled Control Symbol Word None n/a None n/a None n/a None n/a None n/a None n/a None n/a None n/a Control word ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT CONTROL WORD FUNCTIONS The following sections describe the contents of each control word. RC0: Global Features Control Word Input DBA1 DBA0 DA4 DA3 ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT output disable allows the use of the SSTE32882KA1 in reduced parts count applications such as DDR3 Mini-RDIMMs. When output disable is asserted, all outputs on ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT The IBT control is also located in this control word, with two options of 100Ω or 150Ω which can be selected to adapt to different system scenarios. At ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Input (1) CK DCS C/A Standard (1) Yn QxCSx, QxCKEx, QxODTx Qn(C/A) C/A (1) Yn pre- launch QxCSx, QxCKEx, QxODTx Qn(C/ and Yn left out for ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT RC3: CA Signals Driver Characteristics Control Word Input DBA1 DBA0 DA4 DA3 ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT RC5: CK Driver Characteristics Control Word Input DBA1 DBA0 DA4 DA3 ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT RC9: Power Saving Settings Control Word Input DBA1 DBA0 DA4 DA3 ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT or slow a register can run Input DBA1 DBA0 DA4 DA3 ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Test Circuits and Switching Waveforms Parameter Measurement Information All input pulses are supplied by generators having the following characteristics: 300MHz ≤ PRR ≤ 945 MHz ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT CK CK DCSn QxCSn Yn Yn Refer to “Calculating the virtual V Enabling and disabling the CA outputs must not violate DRAM setup and hold time requirements. Therefore ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT V TT actual waveform 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT OUTPUT OUTPUT AC Level (1.5V) AC Level (1.35V) AC Level for Slew Rate Measurement (DDR3U 1.25V) AC Level (1.25V) 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Error Output Load Circuit and Voltage Measurement Information All input pulses are supplied by generators having the following characteristics: 300MHz ≤ PRR ≤ 945 MHz ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT The output driver characteristics are separately controlled for outputs that are often loaded with twice as many DRAMs as the other outputs. Outputs are grouped as follows: • ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT propagation delay for clock signal (rising CK input clock edge to rising Yn output clock edge). staoff maximum ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Open Drain Output ERROUT Open Drain Output ERROUT VIA R1 CARD V DDQ 1Ω GND VIA CARD Place the 2200pF capacitor close ...

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SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Ordering Information XXXX XX SSTE Package Device Type 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE ...

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SSTE32882KA1 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Discover what IDT know-how can do for you. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San ...

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