FAGD1652248BA Intel, FAGD1652248BA Datasheet

FAGD1652248BA

Manufacturer Part Number

FAGD1652248BA

Description

Manufacturer

Intel

Datasheet

1.FAGD1652248BA.pdf (12 pages)

Specifications of FAGD1652248BA

Operating Temperature (max)

85C

Operating Temperature (min)

-40C

Pin Count

Mounting

Surface Mount

Lead Free Status / RoHS Status

Not Compliant

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General Description

The GD16522 is a high performance

monolithic integrated multi-rate Clock

and Data Recovery (CDR) device appli-

cable for optical communication systems

including:

The GD16522 features:

The device also features an additional

high-speed data input for serial loop-back

diagnostic tests.

MON_REF

DIREFN

SBER0

SBER1

DIREF

SLBIN

SLBIP

SDH STM-16 / 4 / 1

SONET OC-48 / 12 / 3

Gigabit Ethernet

Limiting input amplifier.

Analogue peak level detection circuit.

Digital Loss Of Signal (LOS) monitor

circuit with four selectable threshold

settings.

Consecutive Identical Binary Digit

alarm output.

SDIN

RCIP

RCIN

MON

SDIP

Detect

Peak

Amplifier

Limiting

Amplifier

DEC_ADJ

1/4

REF_SEL

SD_SEL

MUX

BEF

TCK

Frequency

Detect

Phase

Detect

VCTL

Lock

The CDR contains all circuits needed for

reliable acquisition and lock of the VCO

phase to the incoming data-stream.

The electrical input sensitivity is better

than 8 mV (BER <10

The device exceeds all ITU-T and

Bellcore IEEE jitter requirements when

used with the recommended loop filter

(jitter tolerance, -transfer and -genera-

tion).

The output clock (2.488 GHz when

STM-16 data input is selected) is main-

tained within 500 ppm tolerance of the

reference frequency in the absence of

data.

The GD16522 is available in 48 lead

7 × 7 mm TQFP power enhanced plastic

package.

VCO

BRS0

Continuous

CDR_SEL

Detector

Divider

Phase

MUX

B.B

Bit

BRS1

-10

SELTCK

VCC

VCCL

VCCO

VCCP

VCCV

SCOP

SCON

SDOP

SDON

SDOWN_G

SDOWN_L

BC_DET

LOCK_DET

LOS_DET

PCTL

VEE

VEEL

VEEP

VEEV

2.5 Gbit/s

Clock and Data

Recovery

GD16522

Features

Applications

Exceeds ITU-T and Bellcore require-

ments of Jitter Transfer, Generation

and Tolerance.

Integrated Limiting Amplifier.

Digital LOS monitor and alarm output.

Bit Consecutive Detect Output.

Multi-rate data input.

Differential CML data input with inter-

nal 50 W load termination.

Control inputs are LVTTL.

Reference clock selectable:

– 155.52 MHz

– 38.88 MHz

Single supply operation: +3.3 V.

High-speed serial loop-back input.

Output signal shutdown input.

Available in 48 pin TQFP package

(7 × 7 mm).

Clock and Data Recovery for optical

communication systems including:

– SDH STM-16 / 4 / 1

– SONET OC-48 / 12 / 3

– Gigabit Ethernet

Data Sheet Rev.: 21

Related parts for FAGD1652248BA

FAGD1652248BA Summary of contents

Page 1

... Intel company General Description The GD16522 is a high performance monolithic integrated multi-rate Clock and Data Recovery (CDR) device appli- cable for optical communication systems including: SDH STM- SONET OC- Gigabit Ethernet u The GD16522 features: Limiting input amplifier. u Analogue peak level detection circuit. ...

Page 2

Functional Details The main application of the GD16522 receiver for optical communication systems: SDH STM- SONET OC- Gigabit Ethernet u The GD16522 integrates: a Limiting Amplifier u ...

Page 3

LOS_DET The Loss Of Signal DETection (LOS_DET) alarm output is low during normal operation. The LOS_DET signal is the output from a digital Bit Error Flag (BEF) circuit which monitors the number of false bit transi- tions in the data ...

Page 4

From LINE SDIP 50 DIREF VTT 50 DIREFN VTT From LINE SDIN Figure 1. DC Coupled Input (Ignoring internal offset compensation) From LINE SDIP 50 DIREF VEE 50 DIREFN VEE From LINE SDIN Figure 2. AC Coupled Input (Using internal ...

Page 5

Pin List Mnemonic: Pin no.: SDIP, SDIN 8, 6 DIREF, DIREFN 9, 5 SLBIP, SLBIN 11, 10 SDOP, SDON 28, 29 SCOP, SCON 31, 32 RCIP, RCIN 17, 18 DEC_ADJ 1 VCTL 45 MON 48 MON_REF 47 PCTL 41 REF_SEL ...

Page 6

Mnemonic: Pin no.: VEEP 42 VEEV 44 VCC 12, 19, 24, 34, 37 VCCL 2, 3 VCCO 30 VCCP 43 VCCV 46 Pin Outline DEC_ADJ 1 VCCL 2 VCCL 3 VEEL 4 DIREFN 5 SDIN 6 VEEL 7 SDIP 8 ...

Page 7

Maximum Ratings These are the limits beyond which the component may be damaged. All voltages in the table are referred to V All currents in the table are defined positive out of the pin. Symbol: Characteristic: V Power supply CC ...

Page 8

DC Characteristics T = -40 °C to +85 °C. Appropriate heat sink may be required. Device is DC tested in the temperature range 0 ° °C. CASE Specifications from –40 ° °C are guaranteed by design ...

Page 9

AC Characteristics T = -40 °C to +85 °C. Appropriate heat sink may be required. Device is DC tested in the temperature range 0 ° °C. CASE Specifications from –40 ° °C are guaranteed by design ...

Page 10

Jitter ratio Acceptable [ dB ] area - 20M Frequency [ Hz ] Figure 8. Jitter Transfer @ 2.488 Gbit/s. Acceptable 15 Input area Jitter (log) 1.5 [ UIpp ] 0.15 10 600 6k Frequency [ Hz ...

Page 11

Package Outline Figure 10. Package 48 pin TQFP-EDQUAD. All dimensions are in mm. Data Sheet Rev.: 21 GD16522 Page ...

Page 12

... ID>-<Wafer Lot#> <Intel FPO#> <Design ID> Pin 1 - Mark Figure 11. Device Marking. Top View. Ordering Information Please order as specified below: Product Name: Intel Order Number: GD16522-48BA FAGD1652248BA MM#: 836062 an Intel company Mileparken 22, DK-2740 Skovlunde Denmark Phone : +45 7010 1062 Fax : +45 7010 1063 E-mail : sales@giga ...

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