SSTUM32866EC/S-T NXP Semiconductors, SSTUM32866EC/S-T Datasheet - Page 26

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SSTUM32866EC/S-T

Manufacturer Part Number
SSTUM32866EC/S-T
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SSTUM32866EC/S-T

Logic Family
SSTU
Logical Function
Registered Buffer
Number Of Elements
1
Number Of Bits
25
Number Of Inputs
25
Number Of Outputs
25
High Level Output Current
-8mA
Low Level Output Current
8mA
Propagation Delay Time
3ns
Operating Supply Voltage (typ)
1.8V
Operating Supply Voltage (max)
2V
Operating Supply Voltage (min)
1.7V
Clock-edge Trigger Type
Posit/Negat-Edge
Polarity
Non-Inverting
Technology
CMOS
Mounting
Surface Mount
Pin Count
96
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
NXP Semiconductors
14. Abbreviations
15. Revision history
Table 15.
SSTUM32866_1
Product data sheet
Document ID
SSTUM32866_1
Revision history
Release date
20070629
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description” .
Table 14.
Acronym
CMOS
DDR
DIMM
DUT
LVCMOS
PPO
PRR
RDIMM
SSTL
Fig 28. Temperature profiles for large and small components
MSL: Moisture Sensitivity Level
temperature
Abbreviations
Data sheet status
Product data sheet
Description
Complementary Metal Oxide Semiconductor
Double Data Rate
Dual In-line Memory Module
Device Under Test
Low Voltage Complementary Metal Oxide Semiconductor
Partial Parity Out
Pulse Repetition Rate
Registered Dual In-line Memory Module
Stub Series Terminated Logic
Rev. 01 — 29 June 2007
= minimum soldering temperature
1.8 V DDR2-1G configurable registered buffer with parity
maximum peak temperature
minimum peak temperature
= MSL limit, damage level
Change notice
-
SSTUM32866
temperature
Supersedes
-
peak
© NXP B.V. 2007. All rights reserved.
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