SAE81C91N Infineon Technologies, SAE81C91N Datasheet
SAE81C91N
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SAE81C91N Summary of contents
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Microcomputer Components Standalone Full-CAN Controller SAE 81C90/91 Data Sheet 01.97 Preliminary ...
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... Register description and arrangement improved. 1066, 1069 New register maps. 1093 AVLL LLAX DVWH 1093 changed to 5 ns. t WHDX Controller Area Network (CAN): License of Robert Bosch GmbH Semiconductor Group Version 01.97 06.95 05.94 (Copy version) changed to 10 ns. 1 SAE 81C90/91 P-LCC-44-1 P-LCC-28-1 01.97 ...
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Intermediate Version Introduction The Siemens Stand Alone Full CAN (SFCAN) circuit incorporates all the parts for completely autonomous transmission and reception of messages using the CAN protocol. The flexible, programmable interface allows hookup to different implementations of the physical ...
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Pin Configurations (top view) Figure 2 Semiconductor Group 07Feb95@09:05h Intermediate Version 3 SAE 81C90/91 ...
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Intermediate Version Pin Definitions and Functions Symbol Pin Number PLCC-48 PLCC- CLKOUT 14 3 RES 19 4 AD0/ AD1/ AD2/CLK 44 21 AD3 AD4/TIM ...
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Pin Definitions and Functions (cont’d) Symbol Pin Number PLCC-48 PLCC- SSA DD1 DD2 SS1 SS2 1) For best results keep the crystal circuitry connections as ...
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Intermediate Version Functional Description The Siemens stand-alone Full-CAN (SFCAN) circuit is a large-scale-integrated peripheral device that executes the entire protocol of an automobile or industrial network. Figure 3 Block Diagram Semiconductor Group 6 SAE 81C90/91 ...
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Bus communication is based on the controller-area-network (CAN) protocol. With features like short message length, guaranteed reaction time for messages of appropriate priority, which is defined by the message identifiers. Also included are powerful error detection and treatment capabilities plus ...
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Intermediate Version Figure 4 CAM, Message Memory and Time-Stamp Registers Semiconductor Group 8 SAE 81C90/91 ...
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Bit Stream Processor (BSP) The bit-stream processor controls the entire protocol, differentiates between the frames types and detects frame errors. Error Management Logic (EML) The error-management logic receives error messages from the BSP and, in turn, sends back information about ...
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Intermediate Version Time Stamp It is impossible to determine from the received data in the message memory when they were received. So the host controller is unable to derive any information about the actuality or the repetition rate of ...
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Device Control and Registers The operation of the SAE 81C90/91 is controlled via a number of registers. These registers allow initialization and function control, provide status information and configure the message objects. The upper part of the address space provides ...
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Intermediate Version Register Map (ordered by address) Addr. Reg. Name Reset 00 BL1 BL2 BRP RRR1 RRR2 00 ...
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Descriptor Registers A descriptor register is available for each message object and contains the eleven bits of the message identifier (ID.0 through ID.10), the remote-transmission-request bit (RTR) and the data length code (DLC message. DRnH 7 Address: XX ...
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Intermediate Version Descriptor Register Arrangement Address Function 40 High Byte H 41 Low Byte H 42 High Byte H 43 Low Byte High Byte H 5D Low Byte H 5E High Byte H 5F Low ...
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Control Register Summary Register Name Address CTRL 12 H MOD 10 H INT 11 H IMSK 0A H BL1 00 H BL2 01 H BRP 03 H RRR1 04 H RRR2 05 H RIMR1 ...
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Intermediate Version Output-Control Register The output drivers of the SAE 81C90/91’s transmit pins (TXn) can be individually configured. Thus they can be adapted to the requirements of the external bs system Address: 02 OCTP1 OCTN1 H Reset ...
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Output Programming OCTP.n OCTN.n OCP ...
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Intermediate Version Control Register CTRL 7 Address Reset Value Bit(field) Function MM Monitor Mode ’0’: Message object 0 operates like all other objects. ’1’: Message object 0 receives all identifiers that are not ...
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Mode/Status-Register MOD 7 Address: 10 ADE H Reset Value Bit(field) Function IM Init Mode ’0’: Normal mode. ’1’: Initialization mode: write access to the configuration registers BL1, BL2, OC, BRP is enabled. If the bit stays set, ...
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Intermediate Version Notes on Bit TC Scanning this bit is particularly useful if only one transmission is active. If there are several transmission jobs at the same time better to scan the transmit-request register, because bit TC ...
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Interrupt Register INT 7 Address: 11 TCI H Reset Value Bit(field) Function RI Receive Interrupt After a valid message has been received and filed, this bit is set and an interrupt generated. This bit will remain set ...
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Intermediate Version Interrupt-Mask Register These mask bits determine if an event activates the INT pin. They do not influence the INT register. IMSK 7 Address: 0A ETCI H Reset Value Bit(field) Function ERI Enable Receive Interrupt ...
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Bit-Length Registers BL1 7 Address: 00 SAM H Reset Value Bit(field) Function TS1 Length of Timing Segment 1 (TSeg1 (TS1 + 1) TSeg1 TS2 Length of Timing Segment 2 (TSeg2 (TS2 + 1) ...
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Intermediate Version Baud Rate Prescaler Register The register is not readable and can only be written when bit IM (MOD.0) is set. BRPR 7 Address: 03 – H Reset Value Bit(field) Function BRP Baud Rate Prescaler ...
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Receive-Ready Registers RRR2 7 Address: 05 RR15 H Reset Value RRR1 7 Address: 04 RR7 H Reset Value Bit(field) Function RRn Receive Ready Bit ’0’: No new message received in object n. ’1’: A ...
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Intermediate Version Transmit Request Registers The Transmit Request Set Registers provide a transmission request bit (TRSn) for each message object. Setting a transmission request bit causes the respective message transmitted. The bit is cleared by hardware ...
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TRRR2 7 Address: 19 TRR15 H Reset Value TRRR1 7 Address: 18 TRR7 H Reset Value Bit(field) Function TRRx Transmit Request Reset Bit ’0’: No change of the respective transmit request bit. ’1’: The ...
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Intermediate Version Message Time Stamp This mechanism stores the time at which a specific message was received, i.e. it assigns a time stamp to that message. For this purpose the contents of the free-running time stamp counter TSC is ...
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Time Stamp Register Table Address Function 30 High Byte H 31 Low Byte H 32 High Byte H 33 Low Byte High Byte H 3D Low Byte H 3E High Byte H 3F Low Byte H ...
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Intermediate Version Port Control Registers These registers control the parallel ports P0 and P1 which are provided in the SAE 81C90. The Port Direction Registers PxPDR select each port pin separately for input (PxPDR.n=’0’) or output (PxPDR.n=’1’). After reset ...
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Bit Timing A regular bit period is composed of the following three segments: synchronization segment timing segment 1 timing segment 2. The sampling point is between timing segment 1 and timing segment 2. Figure 6 Bit Time Segments Synchronization The ...
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Intermediate Version Figure 7 Lengthening a Bit Period Figure 8 Shortening a Bit Period Delay Times The total delay is calculated from the following single delays: 2 physical bus t (max. 100 ns acc. to CAN specification) Bus t ...
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Host Interfaces There are two different host interfaces implemented in the SAE 81C90/91. Data and addresses on a multiplexed 8-bit bus, compatible with Siemens microcontrollers (C5xx, C16x), can be transferred via the parallel interface (PI). Using the serial synchronous interface ...
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Intermediate Version Figure 9 Serial Interface Timing (for 2 Data Bytes) Semiconductor Group 34 SAE 81C90/91 ...
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Absolute Maximum Ratings Ambient temperature under bias ( T Storage temperature ( )........................................................................................ – 150 ˚ Voltage on pins with respect to ground ( CC Voltage on any pin with respect to ground ( Input ...
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Intermediate Version DC Characteristics – 110 ˚C A Parameter Input low voltage (all except XTAL1 and XTAL2) Input low voltage (XTAL1 and ...
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AC Characteristics (General Timing – 110 ˚C A Parameter Oscillator period Clock input high time Clock input low time Reset pulse width 1) ...
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Intermediate Version Figure 10 SI-Read-Timing (Timing A: Pin TIM = 0) Figure 11 SI-Read-Timing (Timing B: Pin TIM =1) Semiconductor Group 38 SAE 81C90/91 ...
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Figure 12 SI-Write-Timing AC Characteristics (PI Timing – 110 ˚ Parameter Read-Cycle time Write-Cycle time ALE pulse width Address setup to ALE low ...
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Intermediate Version Figure 13 PI Timing: Read-Cycle-Timing Figure 14 PI Timing: Write-Cycle-Timing Semiconductor Group 40 SAE 81C90/91 ...