MT41J128M8JP-125:G Micron Technology Inc, MT41J128M8JP-125:G Datasheet
MT41J128M8JP-125:G
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MT41J128M8JP-125:G Summary of contents
Page 1
... (DDR3-1066) – 1.87ns @ (DDR3-1066) – 2.5ns @ (DDR3-800) – 2.5ns @ (DDR3-800) • Revision RCD- RP-CL RCD (ns) 11-11-11 10-10-10 9-9-9 10-10-10 9-9-9 8-8-8 8-8-8 7-7-7 6-6-6 5-5-5 1 1Gb: x4, x8, x16 DDR3 SDRAM t RP (ns) 13.75 13.75 12.5 12.5 11.25 11. 13.5 13 13.1 13 12.5 12 ...
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... D HX -125F -15E -15F -187 -187E -25 -25E Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 1Gb: x4, x8, x16 DDR3 SDRAM 64 Meg Meg banks (A[12:0]) 8 (BA[2:0]) 8 (BA[2:0]) 1K (A[9:0]) 1K (A[9:0]) : Revision :B/:D/:F Revision Temperature Commercial None Industrial temperature ...
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... DLL Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Input Clock Frequency Change .99 Write Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_TOC.fm - Rev. F 11/08 EN 1Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 ©2006 Micron Technology, Inc. All rights reserved. Table of Contents ...
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... Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry 174 Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit 176 PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_TOC.fm - Rev. F 11/08 EN 1Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 ©2006 Micron Technology, Inc. All rights reserved. ...
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... IH (Command and Address – Clock . VAC for DS (DQ – Strobe . (DQ – Strobe .88 t MRD 108 t MOD 109 Micron Technology, Inc., reserves the right to change products or specifications without notice. 5 1Gb: x4, x8, x16 DDR3 SDRAM List of Figures ©2006 Micron Technology, Inc. All rights reserved. ...
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... Rev. F 11/ RRD (MIN) and RCD (MIN 128 t DQSQ and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 and 137 6 1Gb: x4, x8, x16 DDR3 SDRAM List of Figures Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...
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... Figure 123: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping 180 PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_LOF.fm - Rev. F 11/08 EN 1Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 7 ©2006 Micron Technology, Inc. All rights reserved. ...
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... Rev. F 11/ and . 4R 6ET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DVAC) for CK - CK# and DQS - DQS .45 Characteristics 1. . Characteristics 1.575V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics 1.425V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Gb: x4, x8, x16 DDR3 SDRAM List of Tables Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...
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... DS/ DH – AC/DC-Based . . . . . . . . . . . . . . . . . . . . . (Below for Valid Transition . Micron Technology, Inc., reserves the right to change products or specifications without notice. 9 1Gb: x4, x8, x16 DDR3 SDRAM List of Tables t t IS/ IH – AC/DC-Based78 t t DS/ DH – AC/DC-Based85 ©2006 Micron Technology, Inc. All rights reserved. ...
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... PRE, PREA Writing PRE, PREA Precharging PREA = PRECHARGE ALL READ = RD, RDS4, RDS8 READ AP = RDAP, RDAPS4, RDAPS8 REF = REFRESH RESET = START RESET PROCEDURE SRE = Self refresh entry 10 1Gb: x4, x8, x16 DDR3 SDRAM State Diagram SRE SRX REF Refreshing PDE PDX Precharge power- down ...
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... WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble ...
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... Functional Block Diagrams DDR3 SDRAM is a high-speed, CMOS dynamic random access memory internally configured as an 8-bank DRAM. Figure 3: 256 Meg x 4 Functional Block Diagram ODT ZQ RESET# RZQ ZQCL, ZQCS CKE Control logic A12 CK, CK# BC4 (burst chop) CS# RAS# OTF CAS# WE# ...
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... I/O gating 3 DM mask logic Bank control logic (128 x128) Column decoder Column- 7 address counter/ 3 latch Columns 0, 1, and 2 13 1Gb: x4, x8, x16 DDR3 SDRAM Functional Block Diagrams ODT control V Q NOM Columns 0, 1, and 2 CK, CK# sw1 DLL READ FIFO 8 64 ...
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... DQS NF, DQ4 REF RAS# SS ODT V CAS CS# WE# V BA0 BA2 RESET# A13 SS Micron Technology, Inc., reserves the right to change products or specifications without notice. 14 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions NF, NF/TDQS DM, DM/TDQS SS DD DQ1 DQ3 NF, DQ7 NF, DQ5 CK# V CKE DD A10/AP ...
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... DQS NF, DQ4 REF RAS# SS ODT V CAS CS# WE# V BA0 BA2 A13 RESET Micron Technology, Inc., reserves the right to change products or specifications without notice. 15 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions NF, NF/TDQS DM, DM/TDQS SS DD DQ1 DQ3 NF, DQ7 NF, DQ5 CK# V CKE DD A10/AP ...
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... V Q DQ6 LDQS DQ4 REF RAS# SS ODT V CAS CS# WE# V BA0 BA2 RESET Micron Technology, Inc., reserves the right to change products or specifications without notice. 16 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions DQ12 UDQS# DQ14 UDQS DQ10 DQ8 LDM DQ1 DQ3 ...
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... On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command ...
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... V – No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). – No function: When configured device, these balls are NF. When configured device, these balls are defined as TDQS#, DQ[7:4] ...
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... On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command ...
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... V – No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). – No function: When configured device, these balls are NF. When configured device, these balls are defined as TDQS#, DQ[7:4] ...
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... On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS, and NF/ TDQS# (when TDQS is enabled) for the x8 ...
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... V – No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). Micron Technology, Inc., reserves the right to change products or specifications without notice. 22 1Gb: x4, x8, x16 DDR3 SDRAM Q and DC LOW ≤ ...
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... Rev. F 11/08 EN 0.8 ±0.1 8 ±0.15 Ball 11.5 ±0. 6.4 CTR Micron Technology, Inc., reserves the right to change products or specifications without notice. 23 1Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Ball A1 ID 1.2 MAX 0.25 MIN ©2006 Micron Technology, Inc. All rights reserved. ...
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... PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_D2.fm - Rev. F 11/08 EN 0.8 ±0.1 Ball 11.5 ±0. Micron Technology, Inc., reserves the right to change products or specifications without notice. 24 1Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Ball A1 ID 1.2 MAX 0.25 MIN ©2006 Micron Technology, Inc. All rights reserved. ...
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... PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_D2.fm - Rev. F 11/08 EN 0.8 ±0.1 Ball 15.5 ±0. Micron Technology, Inc., reserves the right to change products or specifications without notice. 25 1Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Ball A1 ID 1.2 MAX 0.25 MIN ©2006 Micron Technology, Inc. All rights reserved. ...
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... PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_D2.fm - Rev. F 11/08 EN 0.8 ±0.1 Ball 15.5 ±0. Micron Technology, Inc., reserves the right to change products or specifications without notice. 26 1Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Ball A1 ID 1.2 MAX 0.25 MIN ©2006 Micron Technology, Inc. All rights reserved. ...
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... Storage temperature STG Notes greater than 0.6 × MAX operating case temperature. T Figure 13 on page 28). 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum T operation. Input/Output Capacitance Table 7: Input/Output Capacitance Note 1 applies to the entire table Capacitance Parameters CK and CK# Δ ...
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... Operating case temperature Junction-to-case (TOP) Notes: 1. MAX operating case temperature. T Figure thermal solution must be designed to ensure the DRAM device does not exceed the maxi- mum T 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum T operation interval refresh rate. The use of SRT or ASR (if available) must be enabled. ...
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... REF DD Measurement Conditions I 0 and 2Ps 4R 5B (see Table 18 on page 38) DD Micron Technology, Inc., reserves the right to change products or specifications without notice. 29 1Gb: x4, x8, x16 DDR3 SDRAM Specifications and Conditions DD measurement tables MIN 2Pf, I 2Q, I 2N, I 3P, and 6ET READ for I ...
Page 30
... ODT and the output buffer is disabled (MR1[12]). 30 1Gb: x4, x8, x16 DDR3 SDRAM Specifications and Conditions DD DDR3-1600 -15 -125F -125E 10-10-10 9-9-9 10-10-10 11-11-11 1.25 ...
Page 31
... DD t RAS (MIN n/a n/a n/a n/a n/a 0 pattern: DD Row addresses switching; Switching Off Disabled n/a All other n/a 31 1Gb: x4, x8, x16 DDR3 SDRAM Specifications and Conditions Operating Current 1 DD One Bank ACTIVATE to READ to PRECHARGE Figure 14 on page 32 HIGH (MIN (MIN ...
Page 32
... Electrical Specifications – 3FF 000 measurement loop DD = 0mA (MR1[12 reflected in this example; however, test conditions are OUT 32 1Gb: x4, x8, x16 DDR3 SDRAM Specifications and Conditions DD T10 T11 T12 T13 T14 T15 T16 3FF 000 PRE Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 33
... Stable Stable Switching Stable Stable Switching Floating Floating Switching Off Off Disabled Disabled n/a n/a None None All All n/a n/a 33 1Gb: x4, x8, x16 DDR3 SDRAM Specifications and Conditions Active Active Standby Power-Down Standby Current Current Current n/a Figure 15 on page 34 ...
Page 34
... PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_D2.fm - Rev. F 11/08 EN Electrical Specifications – 1FFF 2N/I 3N measurement loop 1Gb: x4, x8, x16 DDR3 SDRAM Specifications and Conditions 0000 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. T9 T10 ...
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... Switching; READ command/pattern READ from bank x Column addresses switching; falling DQS Off Disabled 8 fixed (via MR0) All None n/a 35 1Gb: x4, x8, x16 DDR3 SDRAM Specifications and Conditions DD I 4W: Burst Write Operating Current Notes DD – HIGH (MIN n/a n/a n/a n/a n/a ...
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... Electrical Specifications – 3FF 0mA (MR1[12 reflected in this example; however, test conditions are OUT Micron Technology, Inc., reserves the right to change products or specifications without notice. 36 1Gb: x4, x8, x16 DDR3 SDRAM Specifications and Conditions T10 T11 2 3 000 3FF Start measurement loop © ...
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... Floating Floating Floating Floating Disabled Disabled n/a n/a n/a t RFC (MIN) n/a n/a SRT disabled 37 1Gb: x4, x8, x16 DDR3 SDRAM Specifications and Conditions DD 6ET DD I 6ET: Self Refresh Current DD Extended Temperature Range T = 0°C to 95°C C LOW Off, CK and CK# = LOW n/a ...
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... A0 = ACTIVATE bank 0; RA0 = READ with auto precharge bank DESELECT. PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_D2.fm - Rev. F 11/08 EN Electrical Specifications – Micron Technology, Inc., reserves the right to change products or specifications without notice. 38 1Gb: x4, x8, x16 DDR3 SDRAM Specifications and Conditions DD ©2006 Micron Technology, Inc. All rights reserved. ...
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... SRT and ASR are disabled additional 2mA. DD (MAX) = 85° 85°C; ASR and ODT are disabled; SRT is enabled. 39 1Gb: x4, x8, x16 DDR3 SDRAM Specifications DD DDR3-1600 Units 110 120 mA 110 120 mA 105 115 mA ...
Page 40
... V REF Externally generated peak noise (noncommon mode × V percent values are determined to be less than 20 MHz in frequency. DRAM must meet specifica- tions if the DRAM induces additional AC noise greater than 20 MHz in frequency REF level. Externally generated peak noise (noncommon mode percent × V exceed ± ...
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... Input low DC voltage: Logic 0 Input low AC voltage: Logic 0 Notes: 1. All voltages are referenced to V slew rates and setup/hold times are specified at the DRAM ball inputs. 2. Input setup timing parameters ( 3. Input hold timing parameters ( 4. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is 900mV (peak-to-peak) ...
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... DDR3-800 (see Figure 18 on page 43) 0.67 Vns DD (see Figure 19 on page 43) 0.67 Vns SS 42 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC levels with ringback pulse width REF V REF V REF ...
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... Q 0.25 Vns SS SS Maximum amplitude / Maximum amplitude 43 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC DDR3-1066 DDR3-1333 0.4V 0.4V 0.4V 0.4V 0.19 Vns 0.15 Vns 0.19 Vns 0.15 Vns Overshoot area Time (ns) Undershoot area Time (ns) Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... DC and V . Data strobe is referenced extended range (±175mV) is allowed only for the clock. Additionally, the (MIN) SEH Q SEH (MAX) SEL 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC Min Max –400 V + 400 DD 650 850 200 V + 400 400 –200 150 150 DC REF ...
Page 45
... MAX AC half cycle t DVAC) for CK - CK# and DQS - DQS# Slew Rate (V/ns) >4.0 4.0 3.0 2.0 1.9 1.6 1.4 1.2 1.0 <1.0 45 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and CK# DQS - DQS# t DVAC t DVAC (ps )/V IHDIFF AC ILDIFF 350mV 300mV ...
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... MIN and the first crossing Measured Edge From Rising V REF Falling V REF Rising MAX IL DC Falling MIN 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and MIN. Setup ( MAX (see Figure 22 on page 47 Hold ( REF (see Figure 22 on page 47). REF To Calculation MIN MIN - Δ ...
Page 47
... Figure 22: Nominal Slew Rate Definition for Single-Ended Input Signals Setup Hold PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_3.fm - Rev. F 11/08 EN Electrical Specifications – DC and AC ΔTFS ΔTRH ΔTFH Micron Technology, Inc., reserves the right to change products or specifications without notice. 47 1Gb: x4, x8, x16 DDR3 SDRAM ΔTRS MIN MIN IH ...
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... From Rising MAX IL DIFF Falling MIN IH DIFF ΔTF DIFF Micron Technology, Inc., reserves the right to change products or specifications without notice. 48 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC ) MAX and MIN. The nominal slew IH DIFF ( ) MIN and IH DIFF To Calculation MIN IH ...
Page 49
... TT 120Ω is made 120PD240 60Ω is made and R TT 60PD120 40Ω is made and R TT 40PD80 30Ω is made and R TT 30PD60 20Ω is made and R TT 20PD40 49 1Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics turned off turned off OUT Q SS Nom Max See Table 30 on page 50 ...
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... ODT Sensitivity If either the temperature or voltage changes after I/O calibration, the tolerance limits listed in Table 29 on page 49 and Table 30 can be expected to widen according to Tables 31 and 32 on page 51. PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_3.fm - Rev. F 11/08 EN 1Gb: x4, x8, x16 DDR3 SDRAM V Min OUT 0.2 × ...
Page 51
... Extrapolated point at V Extrapolated point at V Extrapolated point at V Extrapolated point at V Extrapolated points ODTL 8 CWN CWN Micron Technology, Inc., reserves the right to change products or specifications without notice. 51 1Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics Max dV × |DV| RZQ/( 12) TT Q(@ calibration) and Max 1 ...
Page 52
... RZQ/2 (120Ω AOF Begin point: Rising edge CK# defined by the end point of ODTL off CK CK# t AON End point: Extrapolated point 1Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics 50mV 100mV 50mV 100mV 50mV 100mV 50mV 100mV 200mV AOF End point: Extrapolated point at V ...
Page 53
... SW End point: Extrapolated point at V Begin point: Rising edge CK# defined by the end point of ODTL CNW t ADC RTT NOM RTT WR 53 1Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics V t AOFPD End point: Extrapolated point RTT NOM ODTL 8 CWN CWN V t ADC ...
Page 54
... Chip in drive mode Output driver OUT percent) and is actually 34.3Ω ± Micron Technology, Inc., reserves the right to change products or specifications without notice. 54 1Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance is defined by the value of the external ON and R ) are defined turned off OUT ...
Page 55
... V Q 30.5 DD 0.8 × 30.5 DD 0.2 × 30.5 ON 34PU DD 0.5 × 30.5 DD 0.8 × 20 1Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance Nom Max 1.0 1.1 1.0 1.1 1.0 1.4 1.0 1.4 1.0 1.1 1.0 1.1 n 100 X = 1.575V, and Table 39 on page 56 for ...
Page 56
... DD Min dTH × |Δ dVH × |ΔV| ON dTM × |Δ dVM × |ΔV| ON dTL × |Δ dVL × |Δ 1Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance Nom Min 8.8 7.9 21.9 19.7 35.0 24.8 35.0 24.8 21.9 19.7 8.8 7.9 ...
Page 57
... Nom Min dTH × |Δ dVH × |ΔV| ON dTM × |Δ dVM × |ΔV| ON dTL × |Δ dVL × |Δ 1Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance Max 1.5 0.13 1.5 0.13 1.5 0.13 Nom Max 1.0 1.1 1.0 1.1 1 ...
Page 58
... Table 44: 40Ω Output Driver Voltage and Temperature Sensitivity Output Characteristics and Operating Conditions The DRAM uses both single-ended and differential output drivers. The single-ended output driver is summarized in Table 45 while the differential output driver is summa- rized in Table 46 on page 59. Table 45: ...
Page 59
... OHDIFF OLDIFF AC MM PUPD Output Q/2. DD Micron Technology, Inc., reserves the right to change products or specifications without notice. 59 1Gb: x4, x8, x16 DDR3 SDRAM Min Max Units –5 +5 µ V/ 150 V + 150 mV REF REF +0.2 × –0.2 × –10 + Q/2) via 25Ω resistor ...
Page 60
... Output Characteristics and Operating Conditions REF 25Ω Q DQS DQS# Timing reference point ZQ RZQ = 240Ω 1Gb: x4, x8, x16 DDR3 SDRAM X Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. MAX output DIFF MAX MIN ...
Page 61
... Figure 33: Nominal Slew Rate Definition for Single-Ended Output Signals PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_3.fm - Rev. F 11/08 EN Output Characteristics and Operating Conditions ( OL AC Slew Rates (Linear Signals) Measured Edge From Rising Falling Δ 1Gb: x4, x8, x16 DDR3 SDRAM ) and for single-ended signals, as shown Calculation Δ ...
Page 62
... Figure 34: Nominal Differential Output Slew Rate Definition for DQS, DQS# PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_3.fm - Rev. F 11/08 EN Output Characteristics and Operating Conditions ( ) and Rates (Linear Signals) Edge From Rising V ( OLDIFF Falling V ( OHDIFF ΔTF DIFF 62 1Gb: x4, x8, x16 DDR3 SDRAM ( ) for differential signals, as shown in Table 48 AC Measured To Calculation ) OHDIFF OHDIFF ) OLDIFF AC ...
Page 63
... Supported CWL settings t Notes: 1. REFI depends The CL and CWL settings result in CL and CWL requirement settings need to be fulfilled. 3. Reserved settings are not allowed. PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_3.fm - Rev. F 11/08 EN 1Gb: x4, x8, x16 DDR3 SDRAM -25E 5-5-5 Symbol Min Max t RCD 12.5 – ...
Page 64
... CK (AVG) Reserved t CK (AVG) 1.875 <2 OPER t CK requirements. When making a selection of Micron Technology, Inc., reserves the right to change products or specifications without notice. 64 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables -187 8-8-8 Min Max Units Notes 15 – – ns 52.5 – ...
Page 65
... CK (AVG) Reserved t CK (AVG) 1.5 <1.875 1 (AVG) Reserved t CK (AVG) 1.5 <1.875 1 OPER t CK requirements. When making a selection of 65 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables -15E -15 9-9-9 10-10-10 Max Min Max – 15 – – 15 – – 51 – × REFI 36 9 × ...
Page 66
... OPER t CK requirements. When making a selection of Micron Technology, Inc., reserves the right to change products or specifications without notice. 66 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables -125 11-11-11 Min Max Units 13.75 – ns 13.75 – ns 48.75 – ...
Page 67
Table 53: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 74 Parameter Clock period average 0°C to 85°C C DLL disable mode T = >85°C ...
Page 68
Table 53: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 74 Parameter Data setup time to Base (specification) DQS, DQS V/ns REF Data hold ...
Page 69
Table 53: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 74 Parameter DQS, DQS# rising to/from rising CK, CK# DQS, DQS# rising to/from rising CK, CK# when ...
Page 70
Table 53: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 74 Parameter DLL locking time CTRL, CMD, ADDR Base (specification) setup to CK,CK V/ns ...
Page 71
Table 53: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 74 Parameter ZQCL command: Long POWER-UP and RESET calibration time operation Normal operation ZQCS command: Short calibration ...
Page 72
Table 53: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 74 Parameter CKE MIN pulse width Command pass disable delay Power-down entry to power-down exit timing Begin ...
Page 73
Table 53: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 74 Parameter R synchronous turn-on delay TT R synchronous turn-off delay TT R turn-on from ODTL on ...
Page 74
... CL (AVG) are the average half clock period over any 200 the maximum deviation in the clock period from the aver- JIT PER the amount the clock period can deviate from one JIT CC 74 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables ≤ T +95°C and +1.5V ±0.075V output buffer selection ...
Page 75
... SDRAM input clock). 23. Single-ended signal parameter. 24. The DRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by the actual jitter error when input clock jitter is pres- ent, even when within specification. This results in each parameter becoming larger. ...
Page 76
... JIT 41. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT turn-off time maximum is when the DRAM buffer is in High-Z. The ODT refer- ence load is shown in Figure 25 on page 51. This output load is used for ODT timings (see Figure 32 on page 60). ...
Page 77
... IH) nominal slew rate for a rising signal is defined as the slew rate between the ( ) MAX and the first crossing MIN and the first crossing of V REF DDR3-1066 DDR3-1333 125 65 200 140 n/a 190 77 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables t IS (base) + Δ t IS. For a valid tran for some time ]/V [ ...
Page 78
... DDR3 SDRAM Speed Bin Tables t IS 175mV IL AC REF DC 1.6 V/ns 1.4 V/ns 1.2 V/ns Δ t Δ t Δ t Δ t Δ ...
Page 79
... AC t Slew Rate (V/ns) VAC at 175mV (ps) >2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 <0.5 79 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables t VAC at 150mV (ps Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...
Page 80
... VAC for IS (Command and Address – Clock REF region Nominal slew rate t VAC Δ MAX REF ΔTF 80 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables VAC Nominal slew rate REF region Δ MIN - V ( Setup slew rate IH AC REF = rising signal ΔTR Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...
Page 81
... IH REF Nominal slew rate Δ MAX REF Hold slew rate = falling signal ΔTR Micron Technology, Inc., reserves the right to change products or specifications without notice. 81 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Nominal slew rate REF region Δ MIN - REF DC = Δ ...
Page 82
... Rev. F 11/ (Command and Address – Clock Nominal line to AC Tangent line t VAC Setup slew rate rising signal ΔTF Setup slew rate falling signal 82 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables VAC Tangent line REF region ΔTR Tangent line ( MIN - ...
Page 83
... IH (Command and Address – Clock REF Tangent line REF ΔTR Tangent line (V Hold slew rate = rising signal Tangent line (V Hold slew rate = falling signal 83 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Nominal line Tangent line Nominal line Δ MAX) REF DC ...
Page 84
... MAX and the first crossing MIN and the first crossing of V REF DDR3-1066 DDR3-1333 25 – 100 – – 30 – 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables t DS. For a valid transition, the input t )/ for some time VAC (see Table ]/ the time of the rising clock transi- AC ...
Page 85
... DQS, DQS# Differential Slew Rate 2.0 V/ns 1.8 V/ns Δ t Δ t Δ t Δ t Δ –4 0 – –10 8 –2 8 –8 85 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables t DS/ 1.6 V/ns 1.4 V/ns 1.2 V/ Δ Δ Δ Δ Δ –1 –10 7 –2 15 –11 –16 –2 –30 t ...
Page 86
... VAC at 175mV (ps) Slew Rate (V/ns) >2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 <0.5 86 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables [ ]) for Valid Transition AC t VAC at 150mV (ps) Min Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 87
... DS (DQ – Strobe region Nominal slew rate t VAC Δ MAX REF Setup slew rate = rising signal ΔTF 87 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables VAC Nominal slew rate REF region Δ MIN - REF DC = ΔTR Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 88
... DH REF Nominal slew rate Δ MAX REF Hold slew rate = falling signal ΔTR Micron Technology, Inc., reserves the right to change products or specifications without notice. 88 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Nominal slew rate REF region Δ MIN - REF DC = Δ ...
Page 89
... PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_3.fm - Rev. F 11/ (DQ – Strobe Nominal to AC Tangent line t VAC Setup slew rate rising signal ΔTF Setup slew rate falling signal 89 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables VAC line Tangent line REF region ΔTR Tangent line ( MIN - V [ ...
Page 90
... Rev. F 11/ (DQ – Strobe REF Tangent line REF ΔTR Tangent line (V Hold slew rate = rising signal Tangent line (V Hold slew rate = falling signal 90 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Nominal line Tangent line Nominal line Δ MAX) REF Δ ...
Page 91
... Micron Technology, Inc., reserves the right to change products or specifications without notice. 91 1Gb: x4, x8, x16 DDR3 SDRAM Commands BA [2:0] An A12 A10 code Row address (RA RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU ©2006 Micron Technology, Inc. All rights reserved. ...
Page 92
... Burst READs or WRITEs cannot be terminated or interrupted. MRS (fixed) and OTF BL/BC are defined in MR0. 9. The purpose of the NOP command is to prevent the DRAM from registering any unwanted commands. A NOP will not terminate an operation that is executing. 10. The DES and NOP commands perform similarly. ...
Page 93
... The ZQCL command triggers the calibration engine inside the DRAM. After calibration is achieved, the cali- brated values are transferred from the calibration engine to the DRAM I/O, which are reflected as updated R The DRAM is allowed a timing window defined by either the full calibration and transfer of values ...
Page 94
... Rev. F 11/08 EN CKE Previous Next Cycle Cycle CS# RAS# CAS# WE CKE Prev Next Symbol Cycle Cycle CS# RAS# CAS# WE WRS4 WRS8 WRAP WRAPS4 WRAPS8 1Gb: x4, x8, x16 DDR3 SDRAM BA [3:0] An A12 RFU RFU RFU RFU RFU RFU H BA [3:0] An A12 RFU RFU RFU ...
Page 95
... However, the precharge period is determined by the last PRECHARGE command issued to the bank. REFRESH REFRESH is used during normal operation of the DRAM and is analogous to CAS#- before-RAS# (CBR) refresh or auto refresh. This command is nonpersistent must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a “ ...
Page 96
... DRAM is targeted, but not guaranteed, to operate similarly to the normal mode with a few notable exceptions: • The DRAM supports only one value of CAS latency ( and one value of CAS WRITE latency (CWL = 6). • DLL disable mode affects the read data clock-to-data strobe relationship ( ...
Page 97
... MR1[0] to “0” to enable the DLL. Wait enable DLL RESET. 4. After another the appropriate values. 5. The DRAM will be ready for its next command in the DLL enable mode after the greater of or function requiring a locked DLL, a delay of fied. A ZQCL command should be issued with the appropriate timings met as well. ...
Page 98
... Due to latency counter and timing restrictions, only and CWL = 6 are DIS t DQSCK starts from the rising clock edge Micron Technology, Inc., reserves the right to change products or specifications without notice. 98 1Gb: x4, x8, x16 DDR3 SDRAM Commands Td0 Te0 Tf0 Tg0 t DLLK SRX 2 ...
Page 99
... Access window of DQS from CK, CK# Input Clock Frequency Change When the DDR3 SDRAM is initialized, it requires the clock to be stable during most normal states of operation. This means that after the clock frequency has been set to the stable state, the clock period is not allowed to deviate except what is allowed for by the clock jitter and spread spectrum clocking (SSC) specifications ...
Page 100
... ODT signal must be continuously registered LOW ensuring R an off state. If the R charge power-down mode, R tered either LOW or HIGH in this case. PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_4.fm - Rev. F 11/08 EN and R _ must remain in an off state. After the DLL lock time, the DRAM Tc1 Ta0 Tb0 Tc0 t CH ...
Page 101
... Note that nonstandard ODT schemes are required. The memory controller using the write leveling procedure must have adjustable delay settings on its DQS strobe to align the rising edge of DQS to the clock at the DRAM pins. This is accomplished when the DRAM asynchronously feeds back the CK status via the DQ bus and samples with the rising edge of DQS. The controller repeatedly delays the DQS strobe until a CK transition from “ ...
Page 102
... Notes: 1. Expected usage if used during write leveling: Case 1 may be used when DRAM are on a dual-rank module and on the rank not being levelized or on any rank of a module not being levelized on a multislotted system. Case 2 may be used when DRAM are on any rank of a module not being levelized on a multislotted system ...
Page 103
... Write Leveling Procedure A memory controller initiates the DRAM write leveling mode by setting MR1[ “1,” assuming the other programable features (MR0, MR1, MR2, and MR3) are first set and the DLL is fully reset and locked. The DQ balls enter the write leveling mode going from a High-Z state to an undefined driving state, so the DQ bus should not be driven ...
Page 104
... Differential DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. The solid line represents DQS; the dotted line represents DQS#. 5. DRAM drives leveling feedback on a prime DQ (DQ0 for x4 and x8). The remaining DQ are driven low and remain in this state throughout the leveling procedure. ...
Page 105
... Tb0 Tc0 NOP NOP NOP NOP t AOF (MIN) ODTL off NOM t AOF (MAX Indicates A Break in Time Scale 105 1Gb: x4, x8, x16 DDR3 SDRAM Tc1 Tc2 Td0 Td1 Te0 NOP MRS NOP Valid NOP t MRD Valid MR1 t MOD Undefined Driving Mode Transitioning Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...
Page 106
... Q may be applied before or at the same time DLLK (512) cycles of clock input are required to lock the DLL DLLK and ZQ have been satisfied, the DDR3 SDRAM will be ready for nor- INIT 106 1Gb: x4, x8, x16 DDR3 SDRAM Q during power ramp also High-Z). All TT ≤ ...
Page 107
... BA2 = L BA2 = 500µs (MIN) t XPR t MRD MR2 MR3 DRAM ready for external commands Micron Technology, Inc., reserves the right to change products or specifications without notice. 107 1Gb: x4, x8, x16 DDR3 SDRAM Operations Tc0 Tb0 Ta0 MRS MRS ZQCL Code Code Code ...
Page 108
... Down Mode" on page 151). 4. For a CAS latency change, The controller must also wait (excluding NOP and DES), as shown in Figure 53 on page 109. The DRAM requires in order to update the requested features, with the exception of DLL RESET, which requires additional time. Until assumed unavailable. ...
Page 109
... Mode" on page 151). Mode Register 0 (MR0) The base register, MR0, is used to define various DDR3 SDRAM modes of operation. These definitions include the selection of a burst length, burst type, CAS latency, oper- ating mode, DLL RESET, write recovery, and precharge power-down mode, as shown in Figure 54 on page 110 ...
Page 110
... Table 68 on page 111. DDR3 only supports 4-bit burst chop and 8-bit burst access modes. Full interleave address ordering is supported for READs, while WRITEs are restricted to nibble (BC4) or word (BL8) boundaries. PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_4.fm - Rev. F 11/08 EN 1Gb: x4, x8, x16 DDR3 SDRAM BA2 BA1 BA0 A13 ...
Page 111
... DLLK) clock cycles before a READ command can be issued. This DQSCK timings (ns) and rounding up a noninteger value to the next integer: WR (cycles [ns]/ CK [ns]). Micron Technology, Inc., reserves the right to change products or specifications without notice. 111 1Gb: x4, x8, x16 DDR3 SDRAM Operations Burst Type = Interleaved (Decimal) Notes ...
Page 112
... The CL is defined by MR0[6:4], as shown in Figure 54 on page 110. CAS latency is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The CL can be set 10. DDR3 SDRAM do not support half-clock latencies. Examples and are shown in Figure 55 internal READ command is registered at clock edge n, and the CAS latency is m clocks, the data will be available nominally coincident with clock edge ...
Page 113
... RZQ/6 (40Ω [NOM RZQ/12 (20Ω [NOM]) n RZQ/8 (30Ω [NOM]) n Reserved Reserved Reserved Reserved 113 1Gb: x4, x8, x16 DDR3 SDRAM _ value (ODT), WRITE LEVELING, POSTED NOM t t MRD and Address bus Mode register 1 (MR1 ODS DLL TT M0 DLL Enable 0 Enable (normal) 1 Disable ...
Page 114
... When the TDQS function is disabled, the DM function is provided, and the TDQS# ball is not used. The TDQS function is available in the x8 DDR3 SDRAM configuration only and must be disabled via the mode register for the x4 and x16 configurations. PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_4 ...
Page 115
... AL is supported to make the command and data bus efficient for sustainable band- widths in DDR3 SDRAM. MR1[4, 3] define the value shown in Figure 57 on page 116. MR1[4, 3] enable the user to program the DDR3 SDRAM with With this feature, the DDR3 SDRAM enables a READ or WRITE command to be issued after the ACTIVATE command for that bank prior to ACTIVATE to READ or WRITE + AL ≥ ...
Page 116
... Auto Self Refresh Dynamic ODT M6 M10 Disabled: Manual disabled Enabled: Automatic 0 1 RZQ RZQ Reserved 116 1Gb: x4, x8, x16 DDR3 SDRAM T11 T12 T13 NOP NOP NOP Indicates A Break in Transitioning Data Time Scale t t MRD and MOD before initiating a subse- A10 ...
Page 117
... In the disabled mode, SRT requires the user to ensure the DRAM never exceeds a T When SRT is enabled, the DRAM self refresh is changed internally from 1X to 2X, regard- less of the case temperature. This enables the user to operate the DRAM beyond the standard 85° ...
Page 118
... SRT or the ASR to ensure self refresh is performed at the 2X rate. SRT forces the DRAM to switch the internal self refresh rate from 1X to 2X. Self refresh is performed at the 2X refresh rate regardless of the case temperature. ASR automatically switches the DRAM’s internal self refresh rate from 1X to 2X. However, while in self refresh mode, ASR enables the refresh rate to automatically adjust between over the supported temperature range ...
Page 119
... MPR register, and bits 1 and 0 determine which mode the MPR is placed in. The basic concept of the multipurpose register is shown in Figure 61 on page 120. If MR3[ “0,” then the MPR access is disabled, and the DRAM operates in normal mode. However, if MR3[ “1,” then the DRAM no longer outputs normal read data but outputs MPR data as defined by MR3[0, 1]. If MR3[ equal to “ ...
Page 120
... MR3[ (MPR on) DQ, DM, DQS, DQS# Normal operation, no MPR transaction All subsequent READs come from the DRAM memory array All subsequent WRITEs go to the DRAM memory array Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 121
... RFU n/a n/a n/a n/a n/a n/a 121 1Gb: x4, x8, x16 DDR3 SDRAM Burst Order and Data Pattern Burst order Predefined pattern Burst order Predefined pattern Burst order Predefined pattern n/a n/a n/a n/a n/a n/a ...
Page 122
Figure 62: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout T0 Ta0 Tb0 Tb1 CK# CK READ 1 Command PREA MRS NOP MOD Bank address 3 Valid 0 2 A[1: ...
Page 123
Figure 63: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout Tc0 CK# CK READ 1 READ 1 Command PREA MRS CCD t MOD Bank address 3 Valid Valid ...
Page 124
Figure 64: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble Tc0 CK# CK READ 1 READ 1 Command PREA MRS CCD t MOD Bank address 3 Valid Valid ...
Page 125
Figure 65: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble Tc0 CK# CK READ 1 READ 1 Command PREA MRS CCD t MOD Bank address 3 Valid Valid ...
Page 126
... A[1: (data burst order is fixed starting at nibble) – (for BL8, burst order is fixed – A12 = 1 (use BL8) • After CL, the DRAM bursts out the predefined read calibration pattern ( • The memory controller repeats the calibration reads until read data capture at memory controller is optimized • ...
Page 127
... All devices connected to the DQ bus should be High-Z during calibration. ACTIVATE Before any READ or WRITE commands can be issued to a bank within the DRAM, a row in that bank must be opened (activated). This is accomplished via the ACTIVATE command, which selects both the bank and the row to be activated. ...
Page 128
... NOP ACT NOP NOP Row Bank ACT NOP ACT NOP Row Row Bank b Bank c t FAW 128 1Gb: x4, x8, x16 DDR3 SDRAM t CCD (MIN). t FAW (MIN) param T10 NOP NOP NOP t RCD Indicates A Break in Time Scale T9 T10 T11 T19 ACT NOP ...
Page 129
... data-out from column n. 2. Subsequent elements of data-out appear in the programmed order following DO n. DQS, DQS# is driven by the DRAM along with the output data. The initial low state on DQS and HIGH state on DQS# is known as the READ preamble ( DQS and the HIGH state on DQS#, coincident with the last data-out element, is known as the READ postamble ( commands have been initiated, the DQ will go High-Z ...
Page 130
... However, the precharge period will be determined by the last PRECHARGE command issued to the bank. If A10 is HIGH when a READ command is issued, the READ with auto precharge function is engaged. The DRAM starts an auto precharge operation on the rising edge which RTP cycles after the READ command. DRAM support a Figure 78 on page 134) ...
Page 131
Figure 70: Consecutive READ Bursts (BL8 CK# CK Command 1 READ NOP NOP NOP t CCD Bank, Address 2 Col n DQS, DQS Notes: 1. NOP commands are shown for ease ...
Page 132
Figure 72: Nonconsecutive READ Bursts CK# CK Command READ NOP NOP NOP NOP Bank a, Address Col DQS, DQS# DQ Notes ...
Page 133
Figure 74: READ (BC4) to WRITE (BC4) OTF CK# CK Command 1 READ NOP NOP NOP READ-to-WRITE command delay = CCD Bank, Address 2 Col n DQS, ...
Page 134
Figure 76: READ to PRECHARGE (BC4 CK# CK Command READ NOP NOP NOP NOP Bank a, Address Col n t RTP DQS, DQS RAS Figure 77: READ to PRECHARGE ( ...
Page 135
... Rev. F 11/08 EN 1Gb: x4, x8, x16 DDR3 SDRAM t DQSQ of the crossing point of DQS, DQS#. t DQSCK of the clock crossing point. The data Q). Prior to data output from the DRAM RPRE. This is known as the READ preamble. t RPST, is one half clock from the last DQS, DQS# transition. ...
Page 136
Figure 79: Data Output Timing – DQSQ and Data Valid Window T0 T1 CK# CK Command 1 READ NOP Bank, Address 2 Col n DQS, DQS (last data valid (first data no longer valid) All ...
Page 137
... LZ (DQS) MIN and HZ (DQS) MIN are not tied (DQS) MAX and HZ (DQS) MAX are not tied to Micron Technology, Inc., reserves the right to change products or specifications without notice. 137 1Gb: x4, x8, x16 DDR3 SDRAM (DQ) or begins driving LZ (DQS (DQS), LZ (DQ) by measuring the ...
Page 138
... Single-ended signal, provided as background information DQS# Single-ended signal, provided as background information DQS - DQS# Resulting differential signal relevant for t RPST specification PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_4.fm - Rev. F 11/ RPRE begins t RPRE CK CK RPST begins 138 1Gb: x4, x8, x16 DDR3 SDRAM RPRE ends RPST RPST ends Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...
Page 139
... WR has been met, as shown in Figure 93 on page 146 and Figure WTR and WR starting time may vary depending on the mode register settings 139 1Gb: x4, x8, x16 DDR3 SDRAM t DQSS (MIN) and Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...
Page 140
... WPST specification PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_4.fm - Rev. F 11/ WPRE begins t WPRE signal relevant for t WPRE specification t WPST T1 t WPST begins 140 1Gb: x4, x8, x16 DDR3 SDRAM WPRE ends WPST ends Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 141
... DQSH t DSS t DSS DQSS t WPRE t DQSH t DQSL t DQSH t DQSL t DSS t DSS Micron Technology, Inc., reserves the right to change products or specifications without notice. 141 1Gb: x4, x8, x16 DDR3 SDRAM Operations NOP NOP NOP t DSH t DSH t WPST t DQSL t DQSH t DQSL t DQSH t DQSL DSH ...
Page 142
Figure 87: Consecutive WRITE (BL8) to WRITE (BL8 CK# CK Command 1 WRITE NOP NOP NOP t CCD Address 2 Valid DQS, DQS Notes: 1. NOP commands are shown for ease ...
Page 143
Figure 89: Nonconsecutive WRITE to WRITE CK# CK Command WRITE NOP NOP NOP NOP Address Valid WL = CWL + DQS, DQS Notes ( data-in ...
Page 144
Figure 91: WRITE to READ (BC4 Mode Register Setting CK# CK Command 1 WRITE NOP NOP Address 3 Valid DQS, DQS Notes: 1. NOP commands are shown for ease of illustration; other commands may be ...
Page 145
Figure 92: WRITE (BC4 OTF) to READ (BC4 OTF CK# CK Command 1 WRITE NOP NOP NOP Address 3 Valid DQS, DQS Notes: 1. NOP commands are shown for ease of ...
Page 146
... WR) is referenced from the first rising clock edge after the last t WR specifies the last burst WRITE cycle until the PRECHARGE Micron Technology, Inc., reserves the right to change products or specifications without notice. 146 1Gb: x4, x8, x16 DDR3 SDRAM Operations T9 T10 T11 ...
Page 147
... The WRITE preamble and postamble are also shown. One clock prior to data input to the DRAM, DQS must be HIGH and DQS# must be LOW. Then for a half clock, DQS is driven LOW (DQS# is driven HIGH) during the WRITE preamble, be kept LOW by the controller after the last data is written to the DRAM during the WRITE postamble, Data setup and hold times are shown in Figure 96 on page 148 ...
Page 148
... First and foremost, the clock must be stable (meeting specifications) when self refresh mode is entered. If the clock remains stable and the frequency is not altered while in self refresh mode, then the DRAM is allowed to exit self refresh mode after than when CKE was registered LOW) ...
Page 149
... T1. If both are disabled in the mode registers, ODT can be a “Don’t Care.” must be met, and no data bursts can be in progress. t ISXR at Tc1. 149 1Gb: x4, x8, x16 DDR3 SDRAM t XSDLL must be satisfied. ODT must Tc0 Tc1 Td0 Te0 t CKSRX Valid ...
Page 150
... Extended Temperature Usage Micron’s DDR3 SDRAM support the optional extended temperature range of 0°C to 95° Thus, the SRT and ASR options must be used at a minimum. C The extended temperature range DRAM must be refreshed externally at 2X (double refresh) anytime the case temperature is above 85°C (and does not exceed 95°C). The external refreshing requirement is accomplished by reducing the refresh period from 64ms to 32ms ...
Page 151
... READ operation as well as synchronous ODT operation. During power-down entry, if any bank remains open after all in-progress commands are complete, the DRAM will be in active power-down mode. If all banks are closed after all in-progress commands are complete, the DRAM will be in precharge power-down mode. ...
Page 152
... ODT must valid state but all other input signals are a “Don’t Care.” If RESET# goes LOW during power-down, the DRAM will switch out of power-down mode and go into the reset state. After CKE is registered LOW, CKE must ...
Page 153
... PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_4.fm - Rev. F 11/ NOP t CPDED t IH tCKEmin t PD Exit power-down NOP t CPDED Exit power-down 153 1Gb: x4, x8, x16 DDR3 SDRAM T4 T5 Ta0 NOP NOP NOP t CKE (MIN) tCKEmin mode Indicates A Break in Time Scale T4 Ta Ta1 Valid 1 NOP NOP ...
Page 154
... WRPDEN t CK earlier if BC4MRS. Micron Technology, Inc., reserves the right to change products or specifications without notice. 154 1Gb: x4, x8, x16 DDR3 SDRAM Operations Ta7 Ta8 Ta9 Ta10 Ta11 NOP NOP CPDED t PD Power-down or self refresh entry Indicates A Break In Transitioning Data Time Scale ...
Page 155
... Ta0 t CL NOP NOP t CPDED RFC (MIN RFC, CKE must remain HIGH until Micron Technology, Inc., reserves the right to change products or specifications without notice. 155 1Gb: x4, x8, x16 DDR3 SDRAM Operations Ta7 Tb0 Tb1 Tb2 Tb3 NOP NOP NOP NOP t IS ...
Page 156
... CL NOP NOP t CPDED t IS tCKE NOP NOP t CPDED t IS Micron Technology, Inc., reserves the right to change products or specifications without notice. 156 1Gb: x4, x8, x16 DDR3 SDRAM Operations Don’t Care Don’t Care ©2006 Micron Technology, Inc. All rights reserved. ...
Page 157
... NOP t MRSPDEN NOP NOP Exit power-down mode Micron Technology, Inc., reserves the right to change products or specifications without notice. 157 1Gb: x4, x8, x16 DDR3 SDRAM Operations Ta2 Ta3 t CPDED NOP t PD Indicates A Break in Time Scale Ta0 Ta1 REFRESH NOP XPDLL 2 Enter power-down ...
Page 158
... HIGH. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power up were executed (see Figure 109 on page 159). All refresh counters on the DRAM are reset, and data stored in the DRAM is assumed unknown after RESET# has gone LOW. PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_4 ...
Page 159
... Code Code BA0 = L BA0 = H BA1 = H BA1 = H BA2 = L BA2 = L t XPR t MRD t MRD MR2 MR3 DRAM ready for external commands 159 1Gb: x4, x8, x16 DDR3 SDRAM Tb0 Tc0 Ta0 Valid Valid Valid MRS MRS ZQCL Code Code Code Code A10 = H BA0 = H BA0 = L ...
Page 160
... On-Die Termination (ODT) ODT is a feature that enables the DRAM to enable/disable and turn on/off termination resistance for each DQ, DQS, DQS#, and DM for the x4 and x8 configurations (and TDQS, TDQS# for the x8 configuration, when enabled). ODT is applied to each DQ, UDQS, UDQS#, LDQS, LDQS#, UDM, and LDM signal for the x16 configuration. ...
Page 161
... The R mentioned. DDR3 SDRAM supports multiple R can and RZQ is 240Ω. R the DRAM is initialized, calibrated, and not performing read access or when it is not in self refresh mode. Write accesses use R during writes, only RZQ/2, RZQ/4, and RZQ/6 are allowed (see Table 78 on page 163). ...
Page 162
... Dynamic ODT In certain application cases, and to further enhance signal integrity on the data bus desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command, essentially changing the ODT termination on the fly. With dynamic ODT (R dynamic ODT (R to nominal ODT (R ...
Page 163
... Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 163 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT ...
Page 164
Figure 111: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 CK# CK Command NOP NOP NOP NOP WRS4 Address Valid ODTH4 ODT ODTL DQS, DQS# DQ Notes: 1. Via MRS ...
Page 165
Figure 113: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 CK# CK NOP WRS8 NOP Command ODTL CNW Address Valid ODTL ON ODT R TT DQS, DQS# DQ Notes: 1. Via ...
Page 166
... AON (MIN) ODTL 4 CWN NOM _ is enabled Micron Technology, Inc., reserves the right to change products or specifications without notice. 166 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT T10 NOP NOP NOP NOP ODTL off t ADC (MIN NOM t ADC (MAX Transitioning and R _ are enabled ...
Page 167
... Since write latency is made up of CAS WRITE latency (CWL) and ADDITIVE latency (AL), the AL programmed into the mode register (MR1[4, 3]) also applies to the ODT signal. The DRAM’s internal ODT signal is delayed a number of clock cycles defined by the AL relative to the external ODT signal. Thus ODTL on = CWL + and ODTL off = CWL + ...
Page 168
Table 81: Synchronous ODT Parameters Symbol Description ODTL on ODT synchronous turn-on delay ODTL off ODT synchronous turn-off delay ODTH4 ODT minimum HIGH time after ODT assertion or WRITE (BC4) ODTH8 ODT minimum HIGH time after WRITE (BL8) t AON ...
Page 169
Figure 117: Synchronous ODT (BC4 CK# CK CKE Command NOP NOP NOP NOP NOP ODTH4 ODT ODTL Notes NOM 2. ODT ...
Page 170
... ODT Off During READs As the DDR3 SDRAM cannot terminate and drive at the same time least one-half clock cycle before the READ preamble by driving the ODT ball LOW (if either R amble as shown in the example in Figure 118 on page 171. Note: ODT may be disabled earlier and enabled later than shown in Figure 118 on page 171. ...
Page 171
Figure 118: ODT During READs CK# CK Command READ NOP NOP NOP NOP Address Valid ODTL off = CWL + ODT DQS, DQS# DQ Notes: 1. ODT must be ...
Page 172
... Asynchronous ODT Mode Asynchronous ODT mode is available when the DRAM runs in DLL on mode and when either R precharged power-down standby (via MR0[12]). Additionally, ODT operates asynchro- nously when the DLL is synchronizing after being reset. See "Power-Down Mode" on page 151 for definition and guidance over power-down details. ...
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Figure 119: Asynchronous ODT Timing with Fast ODT Transition CK# CK CKE ODT t AONPD (MIN Notes ignored. Table 82: Asynchronous ODT Timing Parameters for All ...
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... Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) There is a transition period around power-down entry (PDE) where the DRAM’s ODT may exhibit either synchronous or asynchronous behavior. This transition period occurs if the DLL is selected to be off when in precharge power-down mode by the setting MR0[12 ...
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... NOP NOP ODT A synchronous DRAM NOM synchronous ODT B asynchronous or synchronous DRAM asynchronous or synchronous ODT C asynchronous DRAM asynchronous Notes CWL = 5; ODTL off = Min Greater of: t Lesser of: AONPD (MIN) (1ns) or × ODTL AON (MIN) t Lesser of: AOFPD (MIN) (1ns) or × ODTL off CK + AOF (MIN) ...
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... Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) The DRAM’s ODT may exhibit either asynchronous or synchronous behavior during power-down exit (PDX). This transition period occurs if the DLL is selected to be off when in precharge power-down mode by setting MR0[12] to “0.” Power-down exit begins ...
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... DRAM NOM asynchronous t AOFPD (MAX) ODT B asynchronous or synchronous asynchronous NOM or synchronous ODT C synchronous DRAM synchronous Notes CWL = 5; ODTL off = Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 NOP NOP NOP NOP NOP NOP NOP t XPDLL PDX transition period ODTL off + t AOF (MIN) ...
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... If the time in the precharge power down or idle states is very short (short CKE LOW pulse), the power-down entry and power-down exit transition periods will overlap. When overlap occurs, the response of the DRAM’ synchronous or asynchronous from the start of the power-down entry transition period to the end of the power-down exit transition period even if the entry period ends later than the exit period (see Figure 122 on page 179) ...
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Figure 122: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping CK# CK Command REF NOP NOP NOP CKE t ANPD Short CKE LOW transition period (R Notes ...
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Figure 123: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping CK# CK Command NOP NOP NOP NOP NOP ANPD Short CKE HIGH transition period (R Notes: 1. ...
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... PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_5.fm - Rev E 11/08 EN 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Micron Technology, Inc., reserves the right to change products or specifications without notice. 181 ...