MT41J128M8JP-125:G Micron Technology Inc, MT41J128M8JP-125:G Datasheet - Page 7
MT41J128M8JP-125:G
Manufacturer Part Number
MT41J128M8JP-125:G
Description
IC DDR3 SDRAM 1GBIT 78FBGA
Manufacturer
Micron Technology Inc
Series
-r
Specifications of MT41J128M8JP-125:G
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
1G (128M x 8)
Speed
800MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
78-TFBGA
Lead Free Status / RoHS Status
Supplier Unconfirmed
Available stocks
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Manufacturer
Quantity
Price
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MT41J128M8JP-125:G
Manufacturer:
MICRON23
Quantity:
1 803
Company:
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MT41J128M8JP-125:G
Manufacturer:
Micron Technology Inc
Quantity:
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Manufacturer:
MICRON/美光
Quantity:
20 000
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- Download datasheet (9Mb)
1Gb: x4, x8, x16 DDR3 SDRAM
List of Figures
Figure 113: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 . . . . 165
Figure 114: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4. . . . . . . . . . . . . 166
Figure 115: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4. . . . . . . . . . . . . 166
Figure 116: Synchronous ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 117: Synchronous ODT (BC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 118: ODT During READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 119: Asynchronous ODT Timing with Fast ODT Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 120: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry . . . . 175
Figure 121: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit. . . . . . 177
Figure 122: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping . . . . . . . . . 179
Figure 123: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping. . . . . . . . . 180
PDF: 09005aef826aa906/Source: 09005aef82a357c3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
7
1Gb_DDR3_LOF.fm - Rev. F 11/08 EN
©2006 Micron Technology, Inc. All rights reserved.
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