ISPLSI 1016E-80LJN LATTICE SEMICONDUCTOR, ISPLSI 1016E-80LJN Datasheet

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ISPLSI 1016E-80LJN

Manufacturer Part Number
ISPLSI 1016E-80LJN
Description
CPLD ispLSI® 1000E Family 2K Gates 64 Macro Cells 84MHz EECMOS Technology 5V 44-Pin PLCC
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet

Specifications of ISPLSI 1016E-80LJN

Package
44PLCC
Family Name
ispLSI® 1000E
Device System Gates
2000
Number Of Macro Cells
64
Maximum Propagation Delay Time
18.5 ns
Number Of User I/os
32
Number Of Logic Blocks/elements
16
Typical Operating Supply Voltage
5 V
Maximum Operating Frequency
84 MHz
Operating Temperature
0 to 70 °C
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
1016e_09
• HIGH-DENSITY PROGRAMMABLE LOGIC
• HIGH-PERFORMANCE E
• IN-SYSTEM PROGRAMMABLE
• OFFERS THE EASE OF USE AND FAST SYSTEM
Features
— 2000 PLD Gates
— 32 I/O Pins, Four Dedicated Inputs
— 96 Registers
— High-Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
— Small Logic Block Size for Random Logic
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Device for Faster Prototyping
— Complete Programmable Device Can Combine Glue
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
— Lead-Free Package Options
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
Machines, Address Decoders, etc.
f
t
Market and Improved Product Quality
Logic and Structured Designs
Minimize Switching Noise
Interconnectivity
max = 125 MHz Maximum Operating Frequency
pd = 7.5 ns Propagation Delay
2
CMOS
®
TECHNOLOGY
1
In-System Programmable High Density PLD
The ispLSI 1016E is a High Density Programmable Logic
Device containing 96 Registers, 32 Universal I/O pins,
four Dedicated Input pins, three Dedicated Clock Input
pins, one Global OE input pin and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1016E offers
5V non-volatile in-system programmability of the logic, as
well as the interconnect to provide truly reconfigurable
systems. A functional superset of the ispLSI 1016
architecture, the ispLSI 1016E device adds a new global
output enable pin.
The basic unit of logic on the ispLSI 1016E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1...B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 1016E device. Each GLB has 18 inputs, a
programmable AND/OR/Exclusive OR array, and four
outputs which can be configured to be either combinatorial
or registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
Functional Block Diagram
Description
A0
A1
A2
A3
A4
A5
A6
A7
Global Routing Pool (GRP)
ispLSI
Logic
Array
D Q
D Q
D Q
D Q
GLB
®
1016E
B 6
B 5
B 4
B 3
B 2
B 1
B 0
B 7
CLK
August 2006
0139C1-isp

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ISPLSI 1016E-80LJN Summary of contents

Page 1

... A functional superset of the ispLSI 1016 architecture, the ispLSI 1016E device adds a new global output enable pin. The basic unit of logic on the ispLSI 1016E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1...B7 (see Figure 1). There are a total of 16 GLBs in the ispLSI 1016E device ...

Page 2

... IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (B0 on the ispLSI 1016E device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device ...

Page 3

... IH o Capacitance (T =25 C, f=1.0 MHz) A SYMBOL PARAMETER C Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance 1 (Commercial/Industrial Clock Capacitance 2 Data Retention Specifications PARAMETER Data Retention Erase/Reprogram Cycles Specifications ispLSI 1016E 1 +1.0V CC +1.0V CC PARAMETER Commercial T = 0° 70°C A Industrial T = -40° 85°C A TYPICAL MINIMUM 20 10000 3 MIN ...

Page 4

... Refer to the Power Consumption CC section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum Specifications ispLSI 1016E Figure 2. Test Load GND to 3.0V -125 ≤ -100, -80 ≤ ...

Page 5

... Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions Section. Specifications ispLSI 1016E Over Recommended Operating Conditions 1 DESCRIPTION ...

Page 6

... ORP Bypass Delay orpbp 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR Adjacent path can only be used by Lattice hard macros. Specifications ispLSI 1016E 1 DESCRIPTION 3 6 -125 ...

Page 7

... Clock Delay, Clock GLB to I/O Cell Global Clock Line iocp Global Reset t 59 Global Reset to GLB and I/O Registers gr 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. Specifications ispLSI 1016E 1 DESCRIPTION 7 -80 -125 -100 MIN. ...

Page 8

... Clock (max) + Reg co + Output gy0(max (#54 + #42 + #56) + (#42) + (#47 + #49) 9 (1.3 + 1.8 + 1.8) + (1.8) + (1.0 + 1.4) 1. Calculations are based upon timing specifications for the ispLSI 1016E- Specifications ispLSI 1016E GRP GLB Feedback Comb 4 PT Bypass #34 Reg 4 PT Bypass GLB Reg Bypass #30 #35 GRP ...

Page 9

... Figure 3. Typical Device Power Consumption vs fmax 130 120 110 100 I CC can be estimated for the ispLSI 1016E using the following equation (mA PTs * 0.52 nets * max freq * 0.004) Where PTs = Number of product terms used in design # of nets = Number of signals used in device Max freq = Highest clock frequency to the device (in MHz) The I CC estimate is based on typical conditions ( ...

Page 10

... SCLK/ Y1/RESET GND 1, 23 VCC 12 Pins have dual function capability. 2. Pins have dual function capability which is software selectable. Specifications ispLSI 1016E TQFP PIN NUMBERS 9, 10, 11, 12, Input/Output Pins - These are the general purpose I/O pins used by the logic 14, 15, 16, array. 22, ...

Page 11

... I/O 28 I/O 29 I/O 30 I/O 31 ispEN 1 SDI/ Pins have dual function capability. 2. Pins have dual function capability which is software selectable. ispLSI 1016E 44-Pin TQFP Pinout Diagram I/O 28 I/O 29 I/O 30 I/O 31 ispEN 1 SDI/ Pins have dual function capability. 2. Pins have dual function capability which is software selectable. ...

Page 12

... ORDERING NUMBER 7.5 ispLSI 1016E-125LJN 7.5 ispLSI 1016E-125LTN44 10 ispLSI 1016E-100LJN 10 ispLSI 1016E-100LTN44 15 ispLSI 1016E-80LJN ispLSI 1016E-80LTN44 15 INDUSTRIAL ORDERING NUMBER 15 ispLSI 1016E-80LJNI 15 ispLSI 1016E-80LTN44I 12 Grade Blank = Commercial I = Industrial Package J = PLCC T44 = TQFP JN = Lead-Free PLCC TN44 = Lead-Free TQFP Power L = Low PACKAGE 44-Pin PLCC ...

Page 13

... Revision History Date Version — 08 August 2006 09 Specifications ispLSI 1016E Change Summary Previous Lattice release. Updated for lead-free package options. 13 ...

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