MC14LC5480SD Freescale, MC14LC5480SD Datasheet

MC14LC5480SD

Manufacturer Part Number
MC14LC5480SD
Description
Manufacturer
Freescale
Type
PCMr
Datasheet

Specifications of MC14LC5480SD

Number Of Channels
1
Gain Control
Adjustable
Number Of Adc's
1
Number Of Dac's
1
Adc/dac Resolution
13b
Package Type
SSOP
Sample Rate
8KSPS
Number Of Adc Inputs
1
Number Of Dac Outputs
1
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Pin Count
20
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
5 V PCM Codec-Filter
pin selectable Mu–Law or A–Law companding, and is offered in 20–pin DIP,
SOG, and SSOP packages. This device performs the voice digitization and
reconstruction as well as the band limiting and smoothing required for PCM
systems. This device is designed to operate in both synchronous and
asynchronous applications and contains an on–chip precision reference
voltage.
encoder section. The encoder section immediately low–pass filters the analog
signal with an active R–C filter to eliminate very high frequency noise from being
modulated down to the passband by the switched capacitor filter. From the
active R–C filter, the analog signal is converted to a differential signal. From this
point, all analog signal processing is done differentially. This allows processing
of an analog signal that is twice the amplitude allowed by a single–ended
design, which reduces the significance of noise to both the inverted and
non–inverted signal paths. Another advantage of this differential design is that
noise injected via the power supplies is a common–mode signal that is
cancelled when the inverted and non–inverted signals are recombined. This
dramatically improves the power supply rejection ratio.
passes the analog signal from 200 Hz to 3400 Hz before the signal is digitized
by the differential compressing A/D converter.
converter. The output of the D/A is low–pass filtered at 3400 Hz and sinX/X
compensated by a differential switched capacitor filter. The signal is then filtered
by an active R–C filter to eliminate the out–of–band energy of the switched
capacitor filter.
including Short Frame Sync, Long Frame Sync, IDL, and GCI timing
environments. This device also maintains compatibility with Motorola’s family of
Telecommunication products, including the MC14LC5472 U–Interface Trans-
ceiver, MC145474/75 S/T–Interface Transceiver, MC145532 ADPCM Trans-
coder, MC145422/26 UDLT–1, MC145421/25 UDLT–2, and MC3419/MC33120
SLIC.
low–power performance and proven capability for complex analog/digital VLSI
functions.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 0.1
5/96
The MC14LC5480 is a general purpose per channel PCM Codec–Filter with
This device has an input operational amplifier whose output is the input to the
After the differential converter, a differential switched capacitor filter band–
The decoder accepts PCM data and expands it using a differential D/A
The MC14LC5480 PCM Codec–Filter accepts a variety of clock formats,
The MC14LC5480 PCM Codec–Filter utilizes CMOS due to its reliable
Pin for Pin Replacement for the MC145480
Single 5 V Power Supply
Typical Power Dissipation of 15 mW, Power–Down of 0.01 mW
Fully–Differential Analog Circuit Design for Lowest Noise
Transmit Band–Pass and Receive Low–Pass Filters On–Chip
Active R–C Pre–Filtering and Post–Filtering
Mu–Law and A–Law Companding by Pin Selection
On–Chip Precision Reference Voltage (1.575 V)
Push–Pull 300
MC145536EVK is the Evaluation Kit that Also Includes the MC145532
ADPCM Transcoder
Power Drivers with External Gain Adjust
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
20
20
20
MC14LC5480
MC14LC5480P
MC14LC5480DW
MC14LC5480SD
1
ORDERING INFORMATION
BCLKR
RO+
RO-
PO+
V DD
PO-
FSR
1
PDI
DR
PI
PIN ASSIGNMENT
1
1
2
3
4
5
6
7
8
9
10
SOG PACKAGE
Order this document
PLASTIC DIP
Plastic DIP
SOG Package
SSOP
DW SUFFIX
CASE 751D
CASE 940C
SD SUFFIX
CASE 738
by MC14LC5480/D
P SUFFIX
20
19
18
17
16
15
14
13
12
11
SSOP
V AG
TI+
TI-
TG
Mu/A
V SS
FST
DT
BCLKT
MCLK

Related parts for MC14LC5480SD

MC14LC5480SD Summary of contents

Page 1

... For More Information On This Product, Go to: www.freescale.com Order this document by MC14LC5480/D MC14LC5480 P SUFFIX PLASTIC DIP CASE 738 SUFFIX SOG PACKAGE 20 CASE 751D 1 SD SUFFIX SSOP CASE 940C 20 1 ORDERING INFORMATION MC14LC5480P Plastic DIP MC14LC5480DW SOG Package MC14LC5480SD SSOP PIN ASSIGNMENT TI ...

Page 2

... The low–pass filter used to at- tenuate these aliasing components is typically called a re- construction or smoothing filter. The MC14LC5480 PCM Codec–Filter has the codec, both presampling and reconstruction filters, a precision voltage reference on–chip, and requires no external components. Go to: www.freescale.com RECEIVE SHIFT DR REGISTER FSR ...

Page 3

... PO+. The PO+ and PO– outputs are differential (push–pull) and capable of driving a 300 3.15 V peak, which is 6.3 V peak–to–peak. The bias voltage and signal reference of this output is the V AG pin. The V AG pin cannot source or sink as much current as this pin, and Go to: www.freescale.com load to ...

Page 4

... The encode process uses the DAC, the voltage reference, and a frame–by–frame autozeroed comparator to implement a successive–approximation con- Go to: www.freescale.com load. This ...

Page 5

... Table 1. PCM Codes for Zero and Full Scale Mu–Law Chord Bits Step Bits Sign Bit Table 2. PCM Codes for Digital mW Mu–Law Chord Bits Step Bits Sign Bit to: www.freescale.com A–Law Chord Bits Step Bits A–Law Chord Bits Step Bits ...

Page 6

... Figure 2d. GCI Interface — BCLKR = 0 (Transmit and Receive Have Common Clocking) Figure 2. Digital Timing Modes for the PCM Data Interface For More Information On This Product DON CARE B2-CHANNEL (FSR = B2-CHANNEL (FSR = 1) Go to: www.freescale.com DON'T CARE DON'T CARE DON CARE DON'T CARE ...

Page 7

... IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (DT), and IDL RX (DR). The IDL interface mode provides access to both the transmit and receive PCM data words with common control clocks of IDL Sync and IDL Clock. In this mode, the Go to: www.freescale.com ...

Page 8

... This device was designed for ease of implementation, but due to the large dynamic range and the noisy nature of the environment for this device (digital switches, radio tele- phones, DSP front–end, etc.) special care must be taken to assure optimum analog transmission performance. Go to: www.freescale.com ...

Page 9

... A less than optimum solution may be to limit the bandwidth of the trace by adding series resistance and/or capaci- tance at the input pin. Go to: www.freescale.com ...

Page 10

... V DD – 0.5 V) — (No Load – 1.5 V) — 3.0 V) PDI = V SS — FST and FSR = PDI = V DD — Symbol out Go to: www.freescale.com Symbol Value V DD – 0 – – – stg – +150 Typ Max 5.0 5. 0.01 0.5 0.05 1.0 ...

Page 11

... TI+, TI– TG, RO+, RO– TG, RO+, and RO– RO+ or RO– RO+ or RO– Transmit Receive Power Drivers PI, PO+, PO– – 0.7 V) – 0.2 Differential Load kHz kHz Go to: www.freescale.com Min Typ Max — 0.1 1.0 10 — — — — 10 — — – 2.0 — ...

Page 12

... Hz — — 1600 to 2600 Hz — — 2600 to 2800 Hz — — 2800 to 3000 Hz — — — — — – to: www.freescale.com A/D D/A Units Min Max Min Max U i – 0.25 + 0.25 – 0.25 + 0.25 dB — 0.03 — 0.03 dB — ...

Page 13

... Delay Time from BCLKT High to DT Data Valid 23 Delay Time from the 8th BCLKT Low to DT Output High Impedance For More Information On This Product, Min LONG FRAME SPECIFIC TIMING SHORT FRAME SPECIFIC TIMING Go to: www.freescale.com Typ Max Unit — 256 — ...

Page 14

... Freescale Semiconductor, Inc MCLK 1 BCLKT 12 11 FST 16 16 MSB DT 1 BCLKR 11 12 FSR MSB DR For More Information On This Product CH1 CH2 CH3 ST1 CH1 CH2 CH3 ST1 Figure 3. Long Frame Sync Timing Go to: www.freescale.com ST2 ST3 LSB ST2 ST3 LSB ...

Page 15

... Freescale Semiconductor, Inc MCLK 12 1 BCLKT FST 22 MSB DT 1 BCLKR FSR 13 MSB DR For More Information On This Product CH1 CH2 CH3 ST1 CH1 CH2 CH3 ST1 Figure 4. Short Frame Sync Timing Go to: www.freescale.com ST2 ST3 LSB ST2 ST3 LSB ...

Page 16

... For More Information On This Product, Characteristics ST1 ST2 ST3 LSB MSB CH1 CH2 37 ST1 ST2 ST3 LSB MSB CH1 CH2 Figure 5. IDL Interface Timing Go to: www.freescale.com Min Max Note 2 20 — 60 — 256 4096 50 — 50 — 20 — 75 — — CH3 ST1 ...

Page 17

... Characteristics CH3 ST1 ST2 ST3 LSB MSB CH1 52 CH3 ST1 ST2 ST3 LSB MSB CH1 MSB CH1 53 CH1 Figure 6. GCI Interface Timing Go to: www.freescale.com Min Max Note 2 512 6176 50 — 50 — 20 — 60 — — 60 — 60 — — — CH2 CH3 ST1 ...

Page 18

... RO PO- 16 Mu/A PO FSR FST BCLKR BCLKT 11 PDI MCLK RO FSR FST BCLKR BCLKT 10 11 PDI MCLK Go to: www.freescale.com 0.1 F ANALOG kHz PCM OUT 2.048 MHz PCM ANALOG kHz PCM OUT 2.048 MHz PCM IN ...

Page 19

... Figure 9. Long Frame Sync Clock Circuit for 2.048 MHz SIDETONE 1 RO PO- REC 5 PO FSR 0 BCLKR 10 PDI Figure 10. MC14LC5480 Analog Interface to Handset with IDL Clocking For More Information On This Product, Go to: www.freescale.com 2.048 MHz 300 OSC IN OSC OSC OUT 1 OUT 2 MC74HC4060 1/2 MC74HC73 0.1 F ...

Page 20

... For More Information On This Product PO FSR BCLKR 10 PDI Telephone Line with GCI Clocking 1 RO RO- 1 PO FSR BCLKR 10 PDI Go to: www.freescale.com TI+ 18 0 FST FSC - 8 kHz out 12 BCLKT DCL - 4.096 MHz 11 MCLK TI+ 18 0 kHz FST 13 PCM OUT ...

Page 21

... Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. 2. Digital code includes inversion of all magnitude bits. For More Information On This Product, Digital Code Sign Chord Chord Chord Step to: www.freescale.com Normalized Decode Step Step Step Levels 8031 4191 2079 1023 495 231 ...

Page 22

... Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. 2. Digital code includes inversion of all even numbered bits. For More Information On This Product, Digital Code Sign Chord Chord Chord Step to: www.freescale.com Normalized Decode Step Step Step Levels 4032 2112 1056 528 264 132 ...

Page 23

... CASE 751D–04 P 10X 0.010 (0.25 SEATING –T– PLANE M Go to: www.freescale.com NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MILLIMETERS DIM MIN MAX ...

Page 24

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...

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