LPC1778FET208,551 NXP Semiconductors, LPC1778FET208,551 Datasheet - Page 82

• Manufacturer Part Number: LPC1778FET208,551
• Description: MCU ARM 512K FLASH 208-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1778FET208,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 165
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-TFBGA
• Processor Series: LPC177x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: SSP, I2S, USB, JTAG, Serial, UART, I2C, SD/MMC
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 165
• Number Of Timers: 4
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 100 mA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6688

NXP Semiconductors
Table 15.
C
[1]
[2]
[3]
[4]
[5]
LPC178X_7X
Objective data sheet
Symbol
t
t
t
BLSLBLSH
BLSHEOW
BLSHDNV
Fig 16. External static memory read/write access (PB = 0)
L
= 30 pF, T
Parameters are shown as RD
Parameters specified for 40 % of V
Latest of address valid, CS LOW, OE LOW, BS LOW (PB = 1).
After End Of Read (EOR): Earliest of CS HIGH, OE HIGH, BLSx HIGH (PB = 1), address invalid.
End Of Write (EOW): Earliest of address invalid, CS HIGH, BLSx HIGH (PB = 1).
BLSx
WE
OE
CS
Dynamic characteristics: Static external memory interface
Parameter
BLS LOW to BLS HIGH time WR
BLS HIGH to end of write
time
BLS HIGH to data invalid
time
A
D
amb
=

40

[1]
C to 85
n

or WD
C, V
RD
RD
DD(IO)
2
DD(REG)(3V3)
n
1
RD
in
for rising edges and 60 % of V
Figure 16
5
Conditions
WR
WR12;
PB = 0
All information provided in this document is subject to legal disclaimers.
RD
10
11
RD
; PB = 0
; PB = 0
5
RD
= 3.0 V to 3.6 V. Values guaranteed by design.
5
as indicated in the Conditions column.
4
Rev. 2 — 27 May 2011
[1]
[5]
EOR
Min
(WAITWR 
WAITWEN + 1) 
T
<tbd>
<tbd>
cy(clk)
RD
RD
6
7
DD(IO)
+ <tbd>
WR
WR
for falling edges.
2
…continued
9
32-bit ARM Cortex-M3 microcontroller
WR
Typ
(WAITWR 
WAITWEN + 1) 
T
<tbd>
<tbd>
WR
cy(clk)
1
10
+ <tbd>
WR
12
WR
11
LPC178x/7x
Max
(WAITWR 
WAITWEN + 1) 
T
<tbd>
<tbd>
EOW
cy(clk)
© NXP B.V. 2011. All rights reserved.
WR
+ <tbd>
002aag214
8
82 of 117
Unit
ns
ns
ns