STM32F207VET6 STMicroelectronics, STM32F207VET6 Datasheet

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STM32F207VET6

Manufacturer Part Number
STM32F207VET6
Description
MCU ARM 512KB FLASH 100LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet

Specifications of STM32F207VET6

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, LIN, MMC, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
132K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-11171

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STM32F207VET6
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USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
Features
April 2011
Core: ARM 32-bit Cortex™-M3 CPU with
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
performance from Flash memory, frequency up
to 120 MHz, memory protection unit,
150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1)
Memories
– Up to 1 Mbyte of Flash memory
– 512 bytes of OTP memory
– Up to 128 + 4 Kbytes of SRAM
– Flexible static memory controller that
– LCD parallel interface, 8080/6800 modes
Clock, reset and supply management
– From 1.65 to 3.6 V application supply and
– POR, PDR, PVD and BOR
– 4 to 26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
Low power
– Sleep, Stop and Standby modes
– V
3 × 12-bit, 0.5 µs A/D converters
– up to 24 channels
– up to 6 MSPS in triple interleaved mode
2 × 12-bit D/A converters
General-purpose DMA
– 16-stream DMA controller with centralized
Up to 17 timers
– Up to twelve 16-bit and two 32-bit timers,
Debug mode
– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M3 Embedded Trace Macrocell™
supports Compact Flash, SRAM, PSRAM,
NOR and NAND memories
I/Os
accuracy at 25 °C)
registers, and optional 4 KB backup SRAM
FIFOs and burst support
up to 120 MHz, each with up to 4
IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
BAT
ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM,
supply for RTC, 20 × 32 bit backup
Doc ID 15818 Rev 6
Table 1.
STM32F205xx
STM32F207xx
Reference
LQFP100 (14 × 14 mm)
LQFP176 (24 × 24 mm)
LQFP144 (20 × 20 mm)
LQFP64 (10 × 10 mm)
Up to 140 I/O ports with interrupt capability:
– Up to 136 fast I/Os up to 60 MHz
– Up to 138 5 V-tolerant I/Os
Up to 15 communication interfaces
– Up to 3 × I
– Up to 4 USARTs and 2 UARTs (7.5 Mbit/s,
– Up to 3 SPIs (30 Mbit/s), 2 with muxed I
– 2 × CAN interfaces (2.0B Active)
– SDIO interface
Advanced connectivity
– USB 2.0 full-speed device/host/OTG
– USB 2.0 high-speed/full-speed
– 10/100 Ethernet MAC with dedicated DMA:
8- to 14-bit parallel camera interface: up to
48 Mbyte/s
CRC calculation unit, 96-bit unique ID
Analog true random number generator
ISO 7816 interface, LIN, IrDA, modem
control)
to achieve audio class accuracy via audio
PLL or external PLL
controller with on-chip PHY
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
supports IEEE 1588v2 hardware, MII/RMII
Device summary
STM32F205RB, STM32F205RC, STM32F205RE,
STM32F205RF, STM32F205RG, STM32F205VB,
STM32F205VC, STM32F205VE, STM32F205VF
STM32F205VG, STM32F205ZC, STM32F205ZE,
STM32F205ZF, STM32F205ZG
STM32F207IC, STM32F207IE, STM32F207IF,
STM32F207IG, STM32F207ZC, STM32F207ZE,
STM32F207ZF, STM32F207ZG, STM32F207VC,
STM32F207VE, STM32F207VF, STM32F207VG
2
C interfaces (SMBus/PMBus)
STM32F205xx
STM32F207xx
(10 × 10 mm)
UFBGA176
Part number
FBGA
(0.400 mm pitch)
WLCSP64+2
www.st.com
FBGA
1/163
2
S
1

Related parts for STM32F207VET6

STM32F207VET6 Summary of contents

Page 1

ARM-based 32-bit MCU, 150DMIPs Flash/128+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Features ■ Core: ARM 32-bit Cortex™-M3 CPU with Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution ...

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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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STM32F205xx, STM32F207xx 2.2.29 2.2.30 2.2.31 2.2.32 2.2.33 2.2.34 2.2.35 2.2.36 2.2.37 2.2.38 2.2.39 2.2.40 2.2.41 2.2.42 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . ...

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Contents 5.3.8 5.3.9 5.3.10 5.3.11 5.3.12 5.3.13 5.3.14 5.3.15 5.3.16 5.3.17 5.3.18 5.3.19 5.3.20 5.3.21 5.3.22 5.3.23 5.3.24 5.3.25 5.3.26 5.3.27 5.3.28 6 Package characteristics . . . . . . . . . . . . . . . ...

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STM32F205xx, STM32F207xx List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of tables 2 Table 47 characteristics ...

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STM32F205xx, STM32F207xx List of figures Figure 1. Compatible board design: LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of figures Figure 41. SPI timing diagram - master mode 2 Figure 42 slave timing diagram (Philips protocol) 2 Figure 43 master timing diagram (Philips protocol) Figure 44. USB OTG FS timings: definition of data ...

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STM32F205xx, STM32F207xx Figure 90. OTG HS connection dual-role with external PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Introduction 1 Introduction This datasheet provides the description of the STM32F205xx and STM32F207xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to Section 2.1: Full compatibility throughout the The STM32F205xx and STM32F207xx datasheet should be read in conjunction with the STM32F20x/STM32F21x reference manual. ...

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STM32F205xx, STM32F207xx 2 Description The STM32F205xx and STM32F207xx family is based on the high-performance ARM Cortex™-M3 32-bit RISC core operating at a frequency 120 MHz. The family incorporates high-speed embedded memories (Flash memory Mbyte, ...

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Table 2. STM32F205xx and STM32F207xx features and peripheral counts Peripherals STM32F205Rx Flash memory in 128 256 512 768 Kbytes System 64 96 (SRAM1+S 128(112+16) SRAM in (48+16) (80+16) RAM2) Kbytes Backup 4 FSMC memory No controller Ethernet General- purpose Timers ...

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Table 2. STM32F205xx and STM32F207xx features and peripheral counts (continued) Peripherals STM32F205Rx Operating temperatures LQFP64 LQFP64 LQFP Package LQFP64 WLCSP6 WLCSP 64 4 minimum value of 1. obtained when the device operates in a reduced temperature ...

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Description 2.1 Full compatibility throughout the family The STM32F205xx and STM32F207xx constitute the STM32F20x family whose members are fully pin-to-pin, software and feature compatible, allowing the user to try different memory densities and peripherals for a greater degree of freedom ...

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STM32F205xx, STM32F207xx Figure 2. Compatible board design: LQFP100 Figure 3. Compatible board design: LQFP64 Doc ID 15818 Rev 6 Description Ω resistor ...

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Description 2.2 Device overview Figure 4. STM32F20x block diagram 1. The timers connected to APB2 are clocked from TIMxCLK up to 120 MHz, while the timers connected to APB1 are clocked from TIMxCLK MHz. 16/163 Doc ID ...

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STM32F205xx, STM32F207xx ® 2.2.1 ARM Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU ...

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Description 2.2.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to ...

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STM32F205xx, STM32F207xx 2.2.9 DMA The flexible 16-stream general-purpose DMAs (8 streams for DMA1 and 8 streams for DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to- peripheral transfers. They share some centralized FIFOs for APB/AHB peripherals, support burst transfer and ...

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Description 2.2.11 Nested vectored interrupt controller (NVIC) The STM32F205xx and STM32F207xx embed a nested vectored interrupt controller able to handle maskable interrupt channels (not including the 16 interrupt lines of the Cortex™-M3) and 16 priority levels. ● ...

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STM32F205xx, STM32F207xx 2.2.14 Boot modes At startup, boot pins are used to select one out of three boot options: ● Boot from user Flash ● Boot from system memory ● Boot from embedded SRAM The boot loader is located in ...

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Description 2.2.17 Voltage regulator The regulator has five operating modes: ● Regulator ON – Main regulator mode (MR) – Low power regulator (LPR) – Power-down ● Regulator OFF – Regulator OFF/internal reset ON – Regulator OFF/internal reset OFF Regulator ON ...

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STM32F205xx, STM32F207xx Otherwise, PA0 should be asserted low externally during POR until V 1.8 V (see In this mode, PA0 cannot be used as a GPIO pin since it allows to reset the part of the 1.2 V logic which ...

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Description Figure 7. Startup in regulator OFF: fast V - power-down reset risen before V 2.2.18 Real-time clock (RTC), backup SRAM and backup registers The backup domain of the STM32F205xx and STM32F207xx includes: ● The real-time clock (RTC) ● 4 ...

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STM32F205xx, STM32F207xx 2.2.19 Low-power modes The STM32F205xx and STM32F207xx support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ● Sleep mode In Sleep mode, only the CPU is stopped. ...

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Description 2.2.21 Timers and watchdogs The STM32F205xx and STM32F207xx devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. Table 3 compares the features of the advanced-control, general-purpose and basic timers. Table 3. Timer feature ...

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STM32F205xx, STM32F207xx The TIM1 and TIM8 counters can be frozen in debug mode. Many of the advanced-control timer features are shared with those of the standard TIMx timers which have the same architecture. The advanced-control timer can therefore work together ...

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Description 2.2.23 Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop ...

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STM32F205xx, STM32F207xx Table 4. USART feature comparison USART Standard Modem LIN name features (RTS/CTS) USART1 X X USART2 X X USART3 X X UART4 X - UART5 X - USART6 X X 2.2.28 Serial peripheral interface (SPI) The STM32F20x feature ...

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Description 2.2.30 SDIO An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer MHz in 8-bit mode, and ...

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STM32F205xx, STM32F207xx 2.2.32 Controller area network (CAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended ...

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Description suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: ● Combined Rx and Tx FIFO size of 1024× 35 bits with ...

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STM32F205xx, STM32F207xx alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O alternate function configuration can be locked if needed by following a specific sequence in order to ...

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Description to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is ...

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STM32F205xx, STM32F207xx 3 Pinouts and pin description Figure 8. STM32F20x LQFP64 pinout Figure 9. STM32F20x WLCSP64+2 ballout 1. Top view ...

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Pinouts and pin description Figure 10. STM32F20x LQFP100 pinout 1. RFU means “reserved for future use”. This pin can be tied to V 36/163 ,V or left unconnected Doc ID 15818 Rev 6 STM32F205xx, STM32F207xx ...

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STM32F205xx, STM32F207xx Figure 11. STM32F20x LQFP144 pinout 1. RFU means “reserved for future use”. This pin can be tied left unconnected Doc ID 15818 Rev 6 Pinouts and pin description 37/163 ...

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Pinouts and pin description Figure 12. STM32F20x LQFP176 pinout 1. RFU means “reserved for future use”. This pin can be tied to V 38/163 ,V or left unconnected Doc ID 15818 Rev 6 STM32F205xx, STM32F207xx ...

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STM32F205xx, STM32F207xx Figure 13. STM32F21xxx UFBGA176 ballout PE3 PE2 PE1 PE0 B PE4 PE5 PE6 PB9 C VBAT PI7 PI6 PI5 PC13- PI8- D PI9 PI4 TAMP1 TAMP2 PC14- E PF0 PI10 PI11 OSC32_IN ...

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Pinouts and pin description Table 5. STM32F20x pin and ball definitions (continued) Pins PC14 OSC32_OUT - - - - ...

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STM32F205xx, STM32F207xx Table 5. STM32F20x pin and ball definitions (continued) Pins ...

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Pinouts and pin description Table 5. STM32F20x pin and ball definitions (continued) Pins ...

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STM32F205xx, STM32F207xx Table 5. STM32F20x pin and ball definitions (continued) Pins - - ...

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Pinouts and pin description Table 5. STM32F20x pin and ball definitions (continued) Pins P12 P13 R14 R15 - - 55 ...

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STM32F205xx, STM32F207xx Table 5. STM32F20x pin and ball definitions (continued) Pins - - - 92 111 J14 - - - 93 112 H14 - - - 94 113 G12 - - - 95 114 H13 115 ...

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Pinouts and pin description Table 5. STM32F20x pin and ball definitions (continued) Pins - - - - 130 D13 - - - - 131 E14 - - - - 132 D14 - - - - 133 C14 - - - ...

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STM32F205xx, STM32F207xx Table 5. STM32F20x pin and ball definitions (continued) Pins - - 88 123 151 A11 - - - 124 152 C10 - - - 125 153 B10 - - - 126 154 127 155 ...

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... Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F20x and STM32F21x reference manual, available from the STMicroelectronics website: www.st.com. ...

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Table 6. Alternate function mapping AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 TIM2_CH1 PA0-WKUP TIM 5_CH1 TIM8_ETR TIM2_ETR PA1 TIM2_CH2 TIM5_CH2 PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 PA4 TIM2_CH1 PA5 TIM8_CH1N TIM2_ETR PA6 TIM1_BKIN ...

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Table 6. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 PB15 RTC_50Hz TIM1_CH3N TIM8_CH3N PC0 PC1 PC2 PC3 PC4 PC5 PC6 TIM3_CH1 TIM8_CH1 PC7 TIM3_CH2 TIM8_CH2 PC8 TIM3_CH3 TIM8_CH3 PC9 MCO2 TIM3_CH4 TIM8_CH4 ...

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Table 6. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 PD15 TIM4_CH4 PE0 TIM4_ETR PE1 PE2 TRACECLK PE3 TRACED0 PE4 TRACED1 PE5 TRACED2 TIM9_CH1 PE6 TRACED3 TIM9_CH2 PE7 TIM1_ETR PE8 TIM1_CH1N PE9 TIM1_CH1 ...

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Table 6. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PG10 PG11 PG12 PG13 PG14 PG15 PH0 - OSC_IN PH1 - OSC_OUT PH2 ...

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Table 6. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 PI0 TIM5_CH4 PI1 PI2 TIM8_CH4 PI3 TIM8_ETR PI4 TIM8_BKIN PI5 TIM8_CH1 PI6 TIM8_CH2 PI7 TIM8_CH3 PI8 PI9 PI10 PI11 AF4 AF5 AF6 AF7 ...

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Memory mapping 4 Memory mapping The memory map is shown in Figure 14. Memory map 54/163 Figure 14. Doc ID 15818 Rev 6 STM32F205xx, STM32F207xx ...

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STM32F205xx, STM32F207xx 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...

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Electrical characteristics 5.1.6 Power supply scheme Figure 17. Power supply scheme 1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate ...

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STM32F205xx, STM32F207xx 5.1.7 Current consumption measurement Figure 18. Current consumption measurement scheme 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 8: Current characteristics, and damage to the device. These are stress ratings only and functional ...

Page 58

Electrical characteristics Table 8. Current characteristics Symbol I Total current into V VDD I Total current out of V VSS Output current sunk by any I/O and control pin I IO Output current source by any I/Os and control pin ...

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STM32F205xx, STM32F207xx Table 10. General operating conditions (continued) Symbol Parameter V Internal core voltage to be supplied CAP1 externally in REGOFF mode V CAP2 C Capacitance of external capacitor EXT ESR ESR of external capacitor Power dissipation ...

Page 60

Electrical characteristics Table 11. Limitations depending on the operating power supply range Maximum Operating power ADC supply operation range frequency (f 16 MHz with Conversion V =1 time up to (2) 2.1 V memory wait 1 Msps 18 ...

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STM32F205xx, STM32F207xx Figure 19. Number of wait states versus The supply voltage can drop to 1.65 V when the device operates in a reduced temperature range. 5.3.2 VCAP1/VCAP2 external ...

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Electrical characteristics 5.3.3 Operating conditions at power-up / power-down (regulator ON) Subject to general operating conditions for T Table 12. Operating conditions at power-up / power-down (regulator ON) Symbol VDD V DD 5.3.4 Operating conditions at power-up ...

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STM32F205xx, STM32F207xx 5.3.5 Embedded reset and power control block characteristics The parameters given in temperature and V Table 14. Embedded reset and power control block characteristics Symbol Programmable voltage V PVD detector level selection (2) V PVD hysteresis PVDhyst Power-on/power-down ...

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Electrical characteristics Table 14. Embedded reset and power control block characteristics (continued) Symbol Brownout level 1 V BOR1 threshold Brownout level 2 V BOR2 threshold Brownout level 3 V BOR3 threshold (2) V BOR hysteresis BORhyst (2)(3) T Reset temporization ...

Page 65

STM32F205xx, STM32F207xx Typical and maximum current consumption The MCU is placed under the following conditions: ● At startup, all I/O pins are configured as analog inputs by firmware. ● All peripherals are disabled except explicitly mentioned. ● ...

Page 66

Electrical characteristics Table 16. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM Symbol Parameter Supply current Run mode 1. Code and data processing running ...

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STM32F205xx, STM32F207xx Figure 21. Typical current consumption vs temperature, Run mode, code with data processing running from RAM, and peripherals ON Figure 22. Typical current consumption vs temperature, Run mode, code with data processing running from RAM, and peripherals OFF ...

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Electrical characteristics Figure 23. Typical current consumption vs temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals ON Figure 24. Typical current consumption vs temperature, Run mode, code with data processing running from Flash, ART ...

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STM32F205xx, STM32F207xx Table 17. Typical and maximum current consumption in Sleep mode Symbol Parameter External clock all peripherals enabled Supply current Sleep mode External clock peripherals disabled 1. Based on characterization, tested in production ...

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Electrical characteristics Figure 25. Typical current consumption vs temperature in Sleep mode, peripherals ON Figure 26. Typical current consumption vs temperature in Sleep mode, peripherals OFF 70/163 Doc ID 15818 Rev 6 STM32F205xx, STM32F207xx ...

Page 71

STM32F205xx, STM32F207xx Table 18. Typical and maximum current consumptions in Stop mode Symbol Parameter Flash in Stop mode, low-speed and high-speed internal RC oscillators and high-speed oscillator Supply current OFF (no independent watchdog) in Stop mode with main Flash in ...

Page 72

Electrical characteristics Table 19. Typical and maximum current consumptions in Standby mode Symbol Parameter Backup SRAM ON, RTC ON Supply current Backup SRAM OFF, RTC Standby DD_STBY Backup SRAM ON, RTC OFF mode Backup SRAM OFF, RTC ...

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STM32F205xx, STM32F207xx Table 21. Peripheral current consumption Peripheral AHB1 AHB2 AHB3 (1) (2) Typical consumption at 25 °C GPIO A GPIO B GPIO C GPIO D GPIO E GPIO F GPIO G GPIO H GPIO I OTG_HS + ULPI CRC ...

Page 74

Electrical characteristics Table 21. Peripheral current consumption Peripheral APB1 74/163 (1) (continued) (2) Typical consumption at 25 °C TIM2 TIM3 TIM4 TIM5 TIM6 TIM7 TIM12 TIM13 TIM14 USART2 USART3 UART4 UART5 I2C1 I2C2 I2C3 SPI2 SPI3 CAN1 CAN2 (3) DAC ...

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STM32F205xx, STM32F207xx Table 21. Peripheral current consumption Peripheral APB2 1. TBD stands for “to be defined”. 2. External clock is 25 MHz (HSE oscillator with 25 MHz crystal) and PLL is on. 3. EN1 bit is set in DAC_CR register. ...

Page 76

Electrical characteristics 5.3.8 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in external clock source, and under ambient temperature and supply voltage conditions summarized in Table Table 23. High-speed external user clock ...

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STM32F205xx, STM32F207xx Figure 28. High-speed external clock source AC timing diagram V HSEH 90% 10% V HSEL t r(HSE) External clock source Figure 29. Low-speed external clock source AC timing diagram V LSEH 90% 10% V LSEL t r(LSE) External ...

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Electrical characteristics Table 25. HSE 4-26 MHz oscillator characteristics Symbol f Oscillator frequency OSC_IN R Feedback resistor F Recommended load capacitance C versus equivalent serial resistance of the crystal (R i HSE driving current 2 g Oscillator transconductance m (4) ...

Page 79

STM32F205xx, STM32F207xx Table 26. LSE oscillator characteristics (f Symbol R Feedback resistor F Recommended load capacitance (2) C versus equivalent serial resistance of the crystal (R I LSE driving current 2 g Oscillator Transconductance m (4) t startup time SU(LSE) ...

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Electrical characteristics 5.3.9 Internal clock source characteristics The parameters given in ambient temperature and V High-speed internal (HSI) RC oscillator Table 27. HSI oscillator characteristics Symbol Parameter f Frequency HSI Accuracy of the HSI ACC HSI oscillator HSI oscillator (3) ...

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STM32F205xx, STM32F207xx Low-speed internal (LSI) RC oscillator Table 28. LSI oscillator characteristics Symbol (2) f Frequency LSI (3) t LSI oscillator startup time su(LSI) (3) I LSI oscillator power consumption DD(LSI –40 to ...

Page 82

Electrical characteristics Table 29. Main PLL characteristics (continued) Symbol Parameter t PLL lock time LOCK Cycle-to-cycle jitter Period Jitter (3) Jitter Main clock output (MCO) for Ethernet Main clock output (MCO) for OTG FS Bit Time CAN jitter (4) I ...

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STM32F205xx, STM32F207xx Table 30. PLLI2S (audio PLL) characteristics Symbol Parameter Cycle-to-cycle jitter (4) Jitter Period Jitter Clock output on MCO pin (for Ethernet applications) Clock output on MCO pin (for OTG FS applications) Master I2S clock jitter (5) Jitter WS ...

Page 84

Electrical characteristics 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 31. SSCG parameters constraint Symbol f Mod md MODEPER * INCSTEP 1. Guaranteed by design, not ...

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STM32F205xx, STM32F207xx Figure 34. PLL output clock waveforms in center spread mode Figure 35. PLL output clock waveforms in down spread mode 5.3.12 Memory characteristics Flash memory The characteristics are given at T Table 32. Flash memory characteristics Symbol Parameter ...

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Electrical characteristics Table 33. Flash memory programming Symbol t Word programming time prog t Sector (16 KB) erase time ERASE16KB t Sector (64 KB) erase time ERASE64KB t Sector (128 KB) erase time ERASE128KB t Mass erase time ME V ...

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STM32F205xx, STM32F207xx Table 34. Flash memory programming with V Symbol t Double word programming prog t Sector (16 KB) erase time ERASE16KB t Sector (64 KB) erase time ERASE64KB t Sector (128 KB) erase time ERASE128KB t Mass erase time ...

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Electrical characteristics A device reset allows normal operations to be resumed. The test results are given in defined in application note AN1709. Table 36. EMS characteristics Symbol Voltage limits to be applied on any I/O pin to V FESD induce ...

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STM32F205xx, STM32F207xx Table 37. EMI characteristics Symbol Parameter = 3 120 MHz, code running from Flash with prefetch and cache enabled S Peak level EMI = 3 120 MHz, code running from ...

Page 90

Electrical characteristics Table 39. Electrical sensitivities Symbol Parameter LU Static latch-up class 5.3.15 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below V above V (for standard, 3 V-capable I/O ...

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STM32F205xx, STM32F207xx 5.3.16 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in performed under the conditions summarized in compliant. Table 41. I/O static characteristics Symbol Parameter V Input low level voltage IL (2) TT I/O input ...

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Electrical characteristics All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, ...

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STM32F205xx, STM32F207xx Input/output AC characteristics The definition and values of input/output AC characteristics are given in Table 43, respectively. Unless otherwise specified, the parameters given in performed under the ambient temperature and V in Table 10. Table 43. I/O AC ...

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Electrical characteristics Table 43. I/O AC characteristics OSPEEDRy [1:0] bit Symbol (1) value F Maximum frequency max(IO)out 11 Output high to low level fall t f(IO)out time Output low to high level rise t r(IO)out time Pulse width of external ...

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STM32F205xx, STM32F207xx 5.3.17 NRST pin characteristics The NRST pin input driver uses CMOS technology connected to a permanent pull-up resistor, R (see PU Unless otherwise specified, the parameters given in performed under the ambient temperature and V in ...

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Electrical characteristics 5.3.18 TIM timer characteristics The parameters given in Refer to Section 5.3.16: I/O port characteristics function characteristics (output compare, input capture, external clock, PWM output). Table 45. Characteristics of TIMx connected to the APB1 domain Symbol t Timer ...

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STM32F205xx, STM32F207xx Table 46. Characteristics of TIMx connected to the APB2 domain Symbol t Timer resolution time res(TIM) Timer external clock f EXT frequency on CH1 to CH4 Res Timer resolution TIM 16-bit counter clock period t when internal clock ...

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Electrical characteristics 2 Table 47 characteristics Symbol t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time h(SDA) t r(SDA) SDA and SCL rise time t ...

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STM32F205xx, STM32F207xx 2 Figure 38 bus AC waveforms and measurement circuit 1. Measurement points are done at CMOS levels: 0.3V Table 48. SCL frequency ( External pull-up resistance For speeds around 200 ...

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Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in are derived from tests performed under the ambient temperature, f supply voltage conditions summarized in Refer to Section 5.3.16: I/O port characteristics function characteristics ...

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STM32F205xx, STM32F207xx Figure 39. SPI timing diagram - slave mode and CPHA = 0 NSS input t SU(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA w(SCKL) CPOL=1 t a(SO) MISO OUT su(SI) MOSI I NPUT Figure ...

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Electrical characteristics Figure 41. SPI timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t su(MI) MISO INP UT MOSI OUTUT 1. Measurement points are done at CMOS levels: 0.3V 102/163 ...

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STM32F205xx, STM32F207xx 2 Table 50 characteristics Symbol clock frequency 1/t c(CK r(CK clock rise and fall time t f(CK) ( valid time v(WS) ( hold ...

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Electrical characteristics 2 Figure 42 slave timing diagram (Philips protocol) CPOL = 0 CPOL = 1 WS input SD transmit SD receive 1. Measurement points are done at CMOS levels: 0.3 × LSB transmit/receive of the ...

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STM32F205xx, STM32F207xx USB OTG FS characteristics The USB OTG interface is USB-IF certified (Full-Spee the USB OTG HS and USB OTG FS controllers. Table 51. USB OTG FS startup time Symbol (1) t STARTUP 1. Guaranteed by design, not tested ...

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Electrical characteristics Figure 44. USB OTG FS timings: definition of data signal rise and fall time Differen tial data lines V CRS Table 53. USB OTG FS electrical characteristics Symbol t Rise time r t Fall time ...

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STM32F205xx, STM32F207xx Figure 45. ULPI timing diagram Table 56. ULPI timing Setup time (control in) Output clock Hold time (control in) Output delay (control out) Setup time (control in) Input clock Hold time (control in) (optional) Output delay (control out) ...

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Electrical characteristics Figure 46. Ethernet SMI timing diagram ETH_MDC ETH_MDIO(O) ETH_MDIO(I) Table 58. Dynamics characteristics: Ethernet MAC signals for SMI Symbol t MDC cycle time (1.71 MHz, AHB = 72 MHz) MDC t MDIO write data valid time d(MDIO) t ...

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STM32F205xx, STM32F207xx Table 60 gives the list of Ethernet MAC signals for MII and corresponding timing diagram. Figure 48. Ethernet MII timing diagram MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER MII_TX_CLK MII_TX_EN MII_TXD[3:0] Table 60. Dynamics characteristics: Ethernet MAC signals for MII Symbol ...

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Electrical characteristics 5.3.20 12-bit ADC characteristics Unless otherwise specified, the parameters given in performed under the ambient temperature, f conditions summarized in Table 61. ADC characteristics Symbol Parameter V Power supply DDA V Positive reference voltage REF+ f ADC clock ...

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STM32F205xx, STM32F207xx Table 61. ADC characteristics Symbol Parameter Sampling rate ( MHz) ADC ADC V DC current (4) REF I VREF+ consumption in conversion mode ADC VDDA DC current (4) I DDA consumption in conversion ...

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Electrical characteristics a Table 62. ADC accuracy Symbol ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error 1. Better performance could be achieved in restricted V 2. Based on characterization, not ...

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STM32F205xx, STM32F207xx Figure 50. Typical connection diagram using the ADC R AIN (1) V AIN 1. Refer to Table represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the parasitic pad capacitance ...

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Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in depending on whether V ceramic (good quality). They should be placed them as close as possible to the chip. Figure 51. Power supply and reference ...

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STM32F205xx, STM32F207xx 5.3.21 DAC electrical characteristics Table 63. DAC characteristics Symbol Parameter V Analog supply voltage DDA V Reference supply voltage REF+ V Ground SSA (2) R Resistive load with buffer ON LOAD Impedance output with buffer ( ...

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Electrical characteristics Table 63. DAC characteristics (continued) Symbol Parameter Integral non linearity (difference between measured value at Code i (3) INL and the value at Code line drawn between Code 0 and last Code 1023) Offset error ...

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STM32F205xx, STM32F207xx Figure 53. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. ...

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Electrical characteristics 5.3.24 Embedded reference voltage The parameters given in temperature and V Table 66. Embedded internal reference voltage Symbol V Internal reference voltage REFINT ADC sampling time when (1) T reading the internal reference S_vrefint voltage Internal reference voltage ...

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STM32F205xx, STM32F207xx Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 67. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to ...

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Electrical characteristics Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:0] FSMC_NBL[1:0] FSMC_D[15:0] FSMC_NADV 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 68. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings Symbol t FSMC_NE ...

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STM32F205xx, STM32F207xx Figure 56. Asynchronous multiplexed PSRAM/NOR read waveforms FSMC_NE FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 69. Asynchronous multiplexed PSRAM/NOR read timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NOE low v(NOE_NE) t FSMC_NOE low ...

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Electrical characteristics Figure 57. Asynchronous multiplexed PSRAM/NOR write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 70. Asynchronous multiplexed PSRAM/NOR write timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NWE low v(NWE_NE) t FSMC_NWE low ...

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STM32F205xx, STM32F207xx Synchronous waveforms and timings Figure 58 through Table 74 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● BurstAccessMode = FSMC_BurstAccessMode_Enable; ● MemoryType = FSMC_MemoryType_CRAM; ● WriteBurst = FSMC_WriteBurst_Enable; ...

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Electrical characteristics Table 71. Synchronous multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x = 0...2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x = 0...2) d(CLKL-NExH) t FSMC_CLK low to FSMC_NADV low ...

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STM32F205xx, STM32F207xx Figure 59. Synchronous multiplexed PSRAM write timings Doc ID 15818 Rev 6 Electrical characteristics 125/163 ...

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Electrical characteristics Table 72. Synchronous multiplexed PSRAM write timings Symbol t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-ADV) t d(CLKL-ADIV) t d(CLKL-Data) t su(NWAITV-CLKH) t h(CLKH-NWAITV) t d(CLKL-NBLH) ...

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STM32F205xx, STM32F207xx Figure 60. Synchronous non-multiplexed NOR/PSRAM read timings Table 73. Synchronous non-multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x = 0...2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x = 0...2) ...

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Electrical characteristics Figure 61. Synchronous non-multiplexed PSRAM write timings Table 74. Synchronous non-multiplexed PSRAM write timings Symbol t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-Data) t su(NWAITV-CLKH) t ...

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STM32F205xx, STM32F207xx PC Card/CompactFlash controller waveforms and timings Figure 62 through corresponding timings. The results shown in this table are obtained with the following FSMC configuration: ● COM.FSMC_SetupTime = 0x04; ● COM.FSMC_WaitSetupTime = 0x07; ● COM.FSMC_HoldSetupTime = 0x04; ● COM.FSMC_HiZSetupTime ...

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Electrical characteristics Figure 63. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NREG FSMC_NIOWR FSMC_NIORD t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[15:0] 130/163 High t v(NCE4_1-A) t d(NREG-NCE4_1) t d(NIORD-NCE4_1) t w(NWE) MEMxHIZ =1 t v(NWE-D) Doc ID ...

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STM32F205xx, STM32F207xx Figure 64. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG FSMC_NWE t d(NCE4_1-NOE) FSMC_NOE (1) FSMC_D[15:0] 1. Only data bits 0...7 are read (bits 8...15 are disregarded). t v(NCE4_1-A) High t ...

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Electrical characteristics Figure 65. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[7:0](1) 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 66. PC Card/CompactFlash controller ...

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STM32F205xx, STM32F207xx Figure 67. PC Card/CompactFlash controller waveforms for I/O space write access Table 75. Switching characteristics for PC Card/CF read and write cycles Symbol FSMC_NCEx low (x = 4_1/4_2) to FSMC_Ay valid ( v(NCEx-A) 0...10) FSMC_NCE4_1 low ...

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Electrical characteristics Table 75. Switching characteristics for PC Card/CF read and write cycles Symbol t FSMC_NIOWR low width w(NIOWR) t FSMC_NIOWR low to FSMC_D[15:0] valid v(NIOWR-D) t FSMC_NIOWR high to FSMC_D[15:0] invalid h(NIOWR-D) t FSMC_NCE4_1 low to FSMC_NIOWR valid d(NCE4_1-NIOWR) ...

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STM32F205xx, STM32F207xx Figure 68. NAND controller waveforms for read access Figure 69. NAND controller waveforms for write access Doc ID 15818 Rev 6 Electrical characteristics 135/163 ...

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Electrical characteristics Figure 70. NAND controller waveforms for common memory read access Figure 71. NAND controller waveforms for common memory write access Table 76. Switching characteristics for NAND Flash read and write cycles Symbol (2) t FSMC_D[15:0] valid before FSMC_NWE ...

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STM32F205xx, STM32F207xx Table 76. Switching characteristics for NAND Flash read and write cycles Symbol (3) t FSMC_ALE valid before FSMC_NWE low d(ALE-NWE) (3) t FSMC_NWE high to FSMC_ALE invalid h(NWE-ALE) (3) t FSMC_ALE valid before FSMC_NOE low d(ALE-NOE) (3) t ...

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Electrical characteristics Figure 73. SD default mode Table 78 MMC characteristics Symbol Clock frequency in data transfer f PP mode - SDIO_CK/f t Clock low time, f W(CKL) t Clock high time, f W(CKH) t Clock rise time ...

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STM32F205xx, STM32F207xx 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status ...

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Package characteristics Figure 74. LQFP64 – pin low-profile quad flat package outline Drawing is not to scale. 2. Dimensions are in millimeters. Table 80. LQFP64 – ...

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STM32F205xx, STM32F207xx Figure 76. WLCSP64+2 - 0.400 mm pitch wafer level chip size package outline 1. Drawing is not to scale. Table 81. WLCSP64+2 - 0.400 mm pitch wafer level chip size package mechanical data Symbol Typ A 0.570 A1 ...

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Package characteristics Figure 77. LQFP100 100-pin low-profile quad flat package outline 100 Pin identification e 1. Drawing is not to scale. 2. Dimensions are in millimeters. ...

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STM32F205xx, STM32F207xx Figure 79. LQFP144 mm, 144-pin low-profile quad flat package outline Seating plane ccc 108 109 144 Pin 1 1 identification 1. Drawing is not to scale. ...

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Package characteristics Figure 81. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm, package outline C Seating plane Pin 1 identification 1. Drawing is not to scale. Table 84. LQFP176 - Low profile quad flat package ...

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STM32F205xx, STM32F207xx Figure 82. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline Seating plane Drawing is not to scale. Table 85. UFBGA176+25 - ultra thin ...

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Package characteristics 6.2 Thermal characteristics The maximum chip-junction temperature, T using the following equation: Where: max is the maximum ambient temperature in °C, ● Θ is the package junction-to-ambient thermal resistance, in °C/W, ● JA ● P max ...

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STM32F205xx, STM32F207xx 7 Part numbering Table 87. Ordering information scheme Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 205 = STM32F20x, connectivity, USB OTG FS/HS 207= STM32F20x, connectivity, USB OTG FS/HS, camera interface,, ...

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Application block diagrams Appendix A Application block diagrams A.1 Main applications versus package Table 88 gives examples of configurations for each package. Table 88. Main applications versus package for STM32F20xxx microcontrollers 64 pins Config Config 1 2 OTG X X ...

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STM32F205xx, STM32F207xx A.2 Application example with regulator OFF Figure 83. Regulator OFF/internal reset ON 1. This mode is available only on UFBGA176 and WLCSP64+2 packages. Figure 84. Regulator OFF/ internal reset OFF 1. This mode is available only on WLCSP64+2 ...

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Application block diagrams A.3 USB OTG full speed (FS) interface solutions Figure 85. USB OTG FS peripheral-only connection Figure 86. USB OTG FS host-only connection 1. STMPS2141STR/STULPI01B needed only if the application has to support a V basic power switch ...

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STM32F205xx, STM32F207xx Figure 87. OTG FS connection dual-role with internal PHY 1. External voltage regulator only needed when building STMPS2141STR/STULPI01B needed only if the application has to support a V basic power switch can be used if ...

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Application block diagrams Figure 89. USB OTG HS host-only connection in FS mode 1. STMPS2141STR/STULPI01B needed only if the application has to support a V basic power switch can be used are available on the application board. ...

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STM32F205xx, STM32F207xx A.5 Complete audio player solutions Two solutions are offered, illustrated in Figure 91 shows storage media to audio DAC/amplifier streaming using a software Codec. This solution implements an audio crystal to provide audio class I clock (0.5% error ...

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Application block diagrams Figure 93. Audio player solution using PLL, PLLI2S, USB and 1 crystal Figure 94. Audio PLL (PLLI2S) providing accurate I2S clock 1 MHz CLKIN /M M=1,2,3,..,64 N=192,194,..,432 154/163 PLLI2S 192 to 432 MHz PhaseC VCO /N /R ...

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STM32F205xx, STM32F207xx Figure 95. Master clock (MCK) used to drive the external audio DAC I2S_CK /I2SD 2,3,4,..,129 1. I2S_SCK is the I2S serial clock to the external audio DAC (not to be confused with I2S_CK). Figure 96. Master clock (MCK) ...

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Revision history Revision history Table 89. Document revision history Date Revision 05-Jun-2009 09-Oct-2009 01-Feb-2010 156/163 1 Initial release. Document status promoted from Target specification to Preliminary data. In Table 5: STM32F20x pin and ball – Note 4 updated 2 – ...

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STM32F205xx, STM32F207xx Table 89. Document revision history (continued) Date Revision 13-Jul-2010 Renamed high-speed SRAM, system SRAM. Removed combination: 128 KBytes Flash memory in LQFP144. Added UFBGA176 package. Added note 1 related to LQFP176 package in Table 2, Figure Added information ...

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Revision history Table 89. Document revision history (continued) Date Revision 13-Jul-2010 (continued) 158/163 Added Note 8 for CIO in Table 41: I/O static Updated Section 5.3.18: TIM timer Added T in Table 44: NRST pin NRST_OUT Updated Table 47: I2C ...

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STM32F205xx, STM32F207xx Table 89. Document revision history (continued) Date Revision 25-Nov-2010 Update I/Os in Section : Features. Added WLCSP66(64+2) package. Added note 1 related to LQFP176 on cover page. ART accelerator. Added trademark for Adaptive real-time memory accelerator (ART Updated ...

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Revision history Table 89. Document revision history (continued) Date Revision 22-Apr-2011 160/163 Changed datasheet status to “Full Datasheet”. Introduced concept of SRAM1 and SRAM2. LQFP176 package now in production and offered only for 256 Kbyte and 1 Mbyte devices. Availability ...

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STM32F205xx, STM32F207xx Table 89. Document revision history (continued) Date Revision 22-Apr-2011 (continued) Updated Typical and maximum current consumption well as Table 15: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator ...

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Revision history Table 89. Document revision history (continued) Date Revision 22-Apr-2011 (continued) 162/163 Changed w(SCKH) w(SCLH Table 47: I2C characteristics f(SCK) f(SCL) bus AC waveforms and measurement Added Table 52: USB OTG FS ...

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... STM32F205xx, STM32F207xx Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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