MAX3872ETJ+ Maxim Integrated Products, MAX3872ETJ+ Datasheet

IC DATA RECOVERY W/AMP 32-TQFN

MAX3872ETJ+

Manufacturer Part Number
MAX3872ETJ+
Description
IC DATA RECOVERY W/AMP 32-TQFN
Manufacturer
Maxim Integrated Products
Type
Clock and Data Recovery (CDR)r
Datasheet

Specifications of MAX3872ETJ+

Input
CML
Output
CML
Frequency - Max
2.67GHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-TQFN Exposed Pad
Frequency-max
2.67GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The MAX3872 is a compact, multirate clock and data
recovery with limiting amplifier for OC-3, OC-12, OC-24,
OC-48, OC-48 with FEC SONET/SDH and Gigabit
Ethernet (1.25Gbps/2.5Gbps) applications. Without using
an external reference clock, the fully integrated phase-
locked loop (PLL) recovers a synchronous clock signal
from the serial NRZ data input. The input data is then
retimed by the recovered clock, providing a clean data
output. An additional serial input (SLBI±) is available for
system loopback diagnostic testing. Alternatively, this
input can be connected to a reference clock to maintain a
valid clock output in the absence of data transitions. The
device also includes a loss-of-lock (LOL) output.
The MAX3872 contains a vertical threshold control to
compensate for optical noise due to EDFAs in DWDM
transmission systems. The recovered data and clock
outputs are CML with on-chip 50Ω back termination on
each line. Its jitter performance exceeds all
SONET/SDH specifications.
The MAX3872 operates from a single +3.3V supply and
typically consumes 580mW. It is available in a 5mm x
5mm 32-pin thin QFN with exposed-pad package and
operates over a -40°C to +85°C temperature range.
19-2709; Rev 3; 2/07
Pin Configuration appears at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
SONET/SDH Receivers and Regenerators
Add/Drop Multiplexers
Digital Cross-Connects
SONET/SDH Test Equipment
DWDM Transmission Systems
Access Networks
________________________________________________________________ Maxim Integrated Products
General Description
Multirate Clock and Data Recovery
Applications
FILTER
IN
MAX3745
+3.3V
GND
V
CC
OUT+
OUT-
LOOPBACK DATA
SYSTEM
+3.3V
0.82μF
C
FIL
SDI+
SDI-
SLBI+
SLBI-
V
V
SIS LREF LOL
FIL
CTRL
REF
♦ Multirate Data Input: 2.667Gbps (FEC), 2.488Gbps,
♦ Reference Clock Not Required for Data
♦ Exceeds ANSI, ITU, and Bellcore SONET/SDH
♦ 2.7mUI
♦ 10mV
♦ 0.65UI
♦ ±170mV Input Threshold Adjust Range
♦ Clock Holdover Capability Using Frequency-
♦ Serial Loopback Input Available for System
♦ Loss-of-Lock (LOL) Indicator
with Limiting Amplifier
* EP = Exposed pad.
+ Denotes lead-free package.
MAX3872EGJ
MAX3872ETJ+
VCC_VCO
+3.3V
1.244Gbps, 622.08Mbps, 155.52Mbps,
1.25Gbps/2.5Gbps (Ethernet)
Acquisition
Jitter Specifications
Adjust
Selectable Reference Clock
Diagnostic Testing
+3.3V
PART
MAX3872
CAZ-
RS1
0.1μF
P-P
CAZ
P-P
RMS
CAZ+ FREFSET V
RS2
Input Sensitivity Without Threshold
High-Frequency Jitter Tolerance
RATESET
Typical Application Circuit
+3.3V
Jitter Generation
-40°C to +85°C 32 QFN-EP*
-40°C to +85°C 32 TQFN-EP*
SCLKO+
TEMP RANGE PIN-PACKAGE
SCLKO-
SDO+
GND
SDO-
+3.3V
CC
Ordering Information
CML
CML
Features
G3255-1
T3255-3
CODE
PKG
1

Related parts for MAX3872ETJ+

MAX3872ETJ+ Summary of contents

Page 1

... Input Threshold Adjust Range ♦ Clock Holdover Capability Using Frequency- Selectable Reference Clock ♦ Serial Loopback Input Available for System Diagnostic Testing ♦ Loss-of-Lock (LOL) Indicator Applications PART MAX3872EGJ MAX3872ETJ Exposed pad. + Denotes lead-free package. +3.3V +3.3V CAZ 0.1μF C FIL 0.82μ ...

Page 2

Multirate Clock and Data Recovery with Limiting Amplifier ABSOLUTE MAXIMUM RATINGS Supply Voltage, V ..............................................-0.5V to +5.0V CC Input Voltage Levels (SDI+, SDI-, SLBI+, SLBI-) ..........(V CC Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)............................................±20mA CML Output Current (SDO+, SDO-, SCLKO+, ...

Page 3

Multirate Clock and Data Recovery DC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V -40°C to +85°C. Typical values PARAMETER SYM LVTTL INPUT/OUTPUT SPECIFICATIONS (LOL, LREF, RATESET, RS1, RS2, FREFSET) LVTTL ...

Page 4

Multirate Clock and Data Recovery with Limiting Amplifier AC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V -40°C to +85°C. Typical values are PARAMETER SYM CML OUTPUT SPECIFICATIONS (SDO±, SCLKO±) Output ...

Page 5

Multirate Clock and Data Recovery t CLK SCLKO+ t CLK-Q SDO Figure 3. Definition of Clock-to-Q Delay (V = +3.3V +25°C, unless otherwise noted RECOVERED CLOCK AND DATA 23 (2.488Gbps PATTERN, V 200mV/ ...

Page 6

Multirate Clock and Data Recovery with Limiting Amplifier (V = +3.3V +25°C, unless otherwise noted JITTER TOLERANCE 23 (2.488Gbps PATTERN 10mV IN 100 WITH ADDITIONAL 0.15UI DETERMINISTIC JITTER 10 1 BELLCORE ...

Page 7

Multirate Clock and Data Recovery PIN NAME +3.3V Supply Voltage CC 2 SDI+ Positive Serial Data Input, CML 3 SDI- Negative Serial Data Input, CML 5 SLBI+ Positive System Loopback Input or Reference Clock Input, CML ...

Page 8

Multirate Clock and Data Recovery with Limiting Amplifier Detailed Description The MAX3872 consists of a fully integrated phase- locked loop (PLL), limiting amplifier with threshold adjust, DC-offset cancellation loop, data retiming block, and CML output buffers (Figure 5). The PLL ...

Page 9

Multirate Clock and Data Recovery The phase detector and frequency detector outputs are summed into the loop filter. An external capacitor (C connected from FIL to VCC_VCO is required to set the PLL damping ratio. Note that the PLL jitter ...

Page 10

Multirate Clock and Data Recovery with Limiting Amplifier Table 3. Holdover Frequency Settings REFERENCE CLOCK FREQUENCY (MHz) 666.51 666.51 666.51 622.08/625 622.08/625 622.08 622.08 166.63 166.63 166.63 155.52/156.25 155.52/156.25 155.52 155.52 Setting the Loop Filter The MAX3872 is designed for ...

Page 11

Multirate Clock and Data Recovery Input Terminations The SDI± and SLBI± inputs of the MAX3872 are current- mode logic (CML) compatible. The inputs all provide internal 50Ω termination to reduce the required number of external components. AC-coupling is recommended. See ...

Page 12

Multirate Clock and Data Recovery with Limiting Amplifier +3.3V 0.82μF +3.3V FIL VCC_VCO CAZ- SDI+ TIA OUTPUT MAX3861 (2.488Gbps) AGC AMPLIFIER SDI- SLBI+ MAX3872 SLBI- V CTRL R1 V REF 155.52MHz SIS LREF LOL REFERENCE CLOCK R2 TTL R1 + ...

Page 13

Multirate Clock and Data Recovery (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) ______________________________________________________________________________________ with Limiting Amplifier Package Information 13 ...

Page 14

Multirate Clock and Data Recovery with Limiting Amplifier ((The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline informa- tion www.maxim-ic.com/packages 14 ______________________________________________________________________________________ Package Information (continued) ...

Page 15

... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 © 2007 Maxim Integrated Products ...

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