AD9548BCPZ Analog Devices Inc, AD9548BCPZ Datasheet
AD9548BCPZ
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AD9548BCPZ Summary of contents
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FEATURES Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Auto/manual holdover and reference switchover 4 pairs of reference input pins with each pair configurable as a single differential input or as ...
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AD9548 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Supply Voltage ............................................................................... 4 Supply Current .............................................................................. 4 Power Dissipation ......................................................................... 4 Logic Inputs ...
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Calculating Digital Filter Coefficients ....................................... 107 Calculation of the Register Values ..................................... 108 Calculation of the Register Values ...................................... 108 Calculation of the Register Values ...................................... 109 REVISION HISTORY 10/10—Rev Rev. A Changes to Timing Parameter, Table 17....................................... ...
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AD9548 SPECIFICATIONS Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ) values apply for AVDD3 = DVDD_I/O = 3.3 V; AVDD = DVDD = 1 SUPPLY VOLTAGE ...
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Parameter Incremental Power Dissipation SYSCLK PLL Off Input Reference On Differential Single-Ended Output Distribution Driver On LVDS LVPECL CMOS the frequency at the SYSCLKP and SYSCLKN pins. SYSCLK the sample rate of the output ...
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AD9548 Parameter SYSTEM CLOCK PLL ENABLED PLL Output Frequency Range Phase-Frequency Detector (PFD) Rate Frequency Multiplication Range VCO Gain High Frequency Path Input Frequency Range Minimum Input Slew Rate Frequency Divider Range Common-Mode Voltage Differential Input Voltage Sensitivity Input Capacitance ...
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REFERENCE INPUTS (REFA/REFAA TO REFD/REFDD) Table 8. Parameter DIFFERENTIAL OPERATION Frequency Range Sinusoidal Input LVPECL Input LVDS Input Minimum Input Slew Rate Common-Mode Input Voltage Differential Input Voltage Sensitivity Input Resistance Input Capacitance Minimum Pulse Width High Minimum Pulse Width ...
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AD9548 REFERENCE SWITCHOVER SPECIFICATIONS Table 10. Parameter REFERENCE SWITCHOVER SPECIFICATIONS Maximum Output Phase Perturbation (Phase Build-Out Switchover) Maximum Time/Time Slope (Hitless Switchover) Time Required to Switch to a New Reference Hitless Switchover Phase Build-Out Switchover the frequency ...
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Parameter 1 Rise/Fall Time (20% to 80%) 3.3 V Supply Strong Drive Strength Setting Weak Drive Strength Setting 1.8 V Supply Duty Cycle Output Voltage High ( AVDD3 = 3 AVDD3 = ...
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AD9548 TIME DURATION OF DIGITAL FUNCTIONS Table 13. Parameter TIME DURATION OF DIGITAL FUNCTIONS EEPROM-to-Register Download Time Register-to-EEPROM Upload Time Minimum Power-Down Exit Time Maximum Time from Assertion of the RESET pin to the Pins Entering High ...
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SERIAL PORT SPECIFICATIONS—SPI MODE Table 17. Parameter CS Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SCLK Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input ...
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AD9548 Parameter TIMING SCL Clock Rate Bus-Free Time Between a Stop and Start Condition, t BUF Repeated Start Condition Setup Time, t SU; STA Repeated Hold Time Start Condition, t Stop Condition Setup Time, t SU; STO Low Period of ...
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Parameter 19. 311.04 MHz ; f REF DDS LOOP Bandwidth: 100 Hz to 100 MHz Bandwidth: 5 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 ...
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AD9548 ABSOLUTE MAXIMUM RATINGS Table 20. Parameter Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Digital I/O Supply Voltage (DVDD3) DAC Supply Voltage (AVDD3) Maximum Digital Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DVDD SCLK/SCL SDIO SDO CS/SDA DVDD DVDD3 TCLK TMS TDO TDI DVDD RESET DVDD DVDD NC VSS DACOUTP DACOUTN VSS AVDD3 AVDD3 NOTES CONNECT. 2. THE EXPOSED PAD MUST BE CONNECTED ...
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AD9548 Input/ Pin No. Mnemonic Output 21, 22 AVDD3 I 23, 24 AVDD I 26 CLKINN I 27 CLKINP I 29 AVDD I 30 OUT_RSET O 31, 37, 38, AVDD3 OUT0P O 33 OUT0N O 34, 41 ...
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Input/ Pin No. Mnemonic Output 53 SYSCLKP I 56 AVDD I 57, 58 TDC_VRB, I TDC_VRT 60, 66, 67, AVDD3 REFA I 62 REFAA I 63, 70, 74 AVDD I 64 REFB I ...
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AD9548 TYPICAL PERFORMANCE CHARACTERISTICS f = input reference clock frequency clock frequency loop bandwidth; PLL off = SYSCLK PLL bypassed; PLL on = SYSCLK PLL enabled; I PLL loop filter. AVDD, AVDD3, and DVDD at ...
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INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 20MHz: 361fs (–69.0dBc) –80 20kHz TO 80MHz: 441fs (–67.3dBc) (EXTRAPOLATED) –90 –100 –110 –120 –130 –140 –150 –160 100 1k 10k 100k 1M FREQUENCY OFFSET (Hz) Figure 7. Additive Phase Noise (Output ...
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AD9548 –90 –100 –110 –120 –130 ROHDE & SCHWARZ SMA100 (1GHz) –140 20MHz OCXO –150 –160 ROHDE & SCHWARZ SMA100 (50MHz) –170 100 1k 10k 100k FREQUENCY OFFSET (Hz) Figure 13. Phase Noise of SYSCLK Input Sources 1.0 0.8 LVPECL ...
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LVPECL 110 100 90 80 LVDS 100 200 300 FREQUENCY (MHz) Figure 19. Power Consumption vs. Frequency, LVPECL and LVDS (Single Channel) 160 140 120 20pF LOAD 100 5pF LOAD 10pF LOAD 80 ...
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AD9548 3.5 3.0 20pF LOAD 2.5 2.0 1.5 1.0 0.5 0 –0 TIME (ns) Figure 25. Output Waveform, 3.3 V CMOS (100 MHz, Strong Mode) 2.0 1.5 20pF LOAD 1.0 0.5 0 –0.5 0 ...
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INPUT/OUTPUT TERMINATION RECOMMENDATIONS 0.1µF AD9548 HIGH IMPEDANCE 3.3V LVDS INPUT OUTPUT 0.1µF Figure 28. AC-Coupled LVDS or LVPECL Output Driver AD9548 3.3V LVPECL- COMPATIBLE OUTPUT Figure 29. DC-Coupled LVDS or LVPECL Output Driver 0.1µF AD9548 SELF-BIASED REFERENCE INPUT 0.1µF Figure ...
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AD9548 GETTING STARTED POWER-ON RESET The AD9548 monitors the voltage on the power supplies at power-up. When DVDD3 is greater than 2.35 V ± 0.1 V and DVDD (Pin 1, Pin 6, Pin 12, Pin 77, Pin 83, and Pin ...
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Program the Clock Distribution Outputs The clock distribution parameters reside in the 0400 register address space. They include the following: Output power-down control Output enable (disabled by default) Output synchronization Output mode control Output divider functionality Program the Reference Inputs ...
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AD9548 THEORY OF OPERATION AD9548 REFA DIFFERENTIAL REFAA OR SINGLE-ENDED REFB REFBB REFC DIGITAL PLL CORE REFCC REFD REFDD INPUT REF MONITOR IRQ AND STATUS IRQ LOGIC OVERVIEW The AD9548 provides clocking outputs directly ...
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REFERENCE CLOCK INPUTS Four pairs of pins provide access to the reference clock receivers. Each pair is configurable either as a single differential receiver or as two independent single-ended receivers. To accommodate input signals with slow rising and falling edges, ...
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AD9548 REGISTER CONTROL BITS FORCE VALIDATION TIMEOUT REF MONITOR BYPASS REF MONITOR OVERRIDE REF FAULT REFERENCE MONITOR The main feature to note is that any time faulted = 1, the output latch is reset, which forces valid = 0 (indicating ...
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The MSB of each nibble is the manual profile bit, whereas the three LSBs of each nibble identify one of the eight profiles (0 to 7). A Logic 1 for the manual profile bit assigns the associated reference to the ...
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AD9548 REFERENCE SWITCHOVER An attractive feature of the AD9548 is its versatile reference switchover capability. The flexibility of the reference switchover functionality resides in a sophisticated prioritization algorithm coupled with register-based controls. This scheme provides the user with maximum control ...
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PRIORITY TABLE INPUT COMMON WITHOUT PROMOTION WITH PROMOTION PROFILE SELECTION A/AA B/BB C/CC D/DD Phase Build-Out Reference Switching Phase build-out reference switching is the term given to a reference switchover that completely masks any phase difference ...
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AD9548 DIGITAL PLL (DPLL) CORE DPLL Overview A diagram of the digital PLL core of the AD9584 appears in Figure 37. The phase/frequency detector, feedback path, lock detectors, phase offset, and phase slew rate limiting that comprise this second generation ...
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Address 0313). The 40-bit word is a signed (twos complement) number that represents units of picoseconds. In addition, the user can adjust the closed-loop phase offset (positive or negative) in incremental fashion so, program the ...
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AD9548 draining, the water level in the tub eventually rises above the high water mark (+1024), which causes the phase lock detector to indicate lock. If more draining is taking place than filling, then the water level in the tub ...
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DDS Phase Offset The relative phase of the sinusoid generated by the DDS is numerically controlled by adding a phase offset word to the output of the DDS accumulator. This is accomplished via the open loop phase offset register (Address ...
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AD9548 Note that history accumulation timer = 0 should not be programmed because it may cause improper device operation. The control logic performs a calculation of the average tuning word during the T interval and stores the result in the ...
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The worst-case scenario is maximum f (1 GHz) and minimum f S (62.5 MHz), which yields Δ 2.8 × trillion. Recovery from Holdover When in holdover and a valid reference becomes available, the ...
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AD9548 The LF path permits the user to provide an LVPECL, LVDS, CMOS, or sinusoidal low frequency clock for multiplication by the integrated SYSCLK PLL. The LF path handles input frequencies from 3.5 MHz up to 100 MHz. However, when ...
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To determine the external loop filter components, the user decides on the desired open loop bandwidth (f margin ( ). These parameters allow calculation of the loop filter components, as follows: ⎛ ⎞ ⎜ ⎟ ...
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AD9548 Super-Nyquist Operation Typically, the maximum usable frequency at the DAC output is about 45% of the system clock frequency. However, because sampled DAC, its output spectrum contains Nyquist images. Of particular interest are the images appearing ...
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In addition to the three mode bits, each of the four distribution channel mode registers includes the following control bits: Polarity invert CMOS phase invert Drive strength The polarity invert bit enables the user to choose between normal polarity and ...
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AD9548 Active Reference Synchronization (Zero Delay) Active reference synchronization is the term applied to the case when sync source = 01 (Register 0402, Bits[5:4]). Referring to Figure 48, this means that the active reference sync path is active because Bit ...
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The deterministic delay, expressed as t LATENCY equation is a function of the frequency division factor (Q the channel divider associated with the zero-delay channel × LATENCY n CLK_IN × ...
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AD9548 STATUS AND CONTROL MULTIFUNCTION PINS (M0 TO M7) The AD9548 has eight digital CMOS I/O pins (M0 to M7) that are configurable for a variety of uses. The function of these pins is programmable via the register map. Each ...
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Bits[6:0] Value Output Function 16 Holdover 17 Free run 18 Reset incremental phase offset 19 Increment incremental phase offset 20 Decrement incremental phase offset Unused 32 Override Reference Monitor A 33 Override Reference Monitor AA 34 Override ...
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AD9548 Typically, when the AD9548 asserts the IRQ pin, the user interrogates the IRQ monitor register to identify the source of the interrupt request. After servicing an indicated interrupt, the user should clear the associated IRQ monitor register bit via ...
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Table 26. EEPROM Controller Instruction Set Instruction Bytes Value (Hex) Instruction Type Required Data 3 80 I/O update 1 A0 Calibrate 1 A1 Distribution sync Condition 1 FE Pause 1 FF End 1 ...
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AD9548 A pause instruction, like an end instruction, is stored at the end of a sequence of instructions in the scratch pad. When the controller encounters a pause instruction during an upload sequence, it keeps the EEPROM address pointer at ...
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IF B1 ≤ INSTRUCTION ≤ CF, THEN TAG DECODED CONDITION EEPROM STORE CONDITION INSTRUCTIONS AS THEY ARE READ FROM THE SCRATCH PAD. SCRATCH PAD PROCEDURE The condition is a 5-bit value with 32 possibilities. Condition = 0 is the null ...
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AD9548 Table 27 lists a sample EEPROM download instruction sequence. It illustrates the use of condition instructions and how they alter the download sequence. The table begins with the assumption that no conditions are in effect. That is, the most ...
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SERIAL CONTROL PORT SCLK/SCL CS/SDA SDIO SDO The AD9548 serial control port is a flexible, synchronous serial communications port that provides a convenient interface to many industry-standard microcontrollers and microprocessors. The AD9548 serial control port is compatible with most synchronous ...
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AD9548 SPI Mode Operation The SPI port supports both 3-wire (bidirectional) and 4-wire (unidirectional) hardware configurations and both MSB-first and LSB-first data formats. Both the hardware configuration and data format features are programmable. By default, the AD9548 uses the bidirectional ...
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SPI MSB-/LSB-First Transfers The AD9548 instruction word and payload can be MSB first or LSB first. The default for the AD9548 is MSB first. The LSB-first mode can be set by writing Register 0000, Bit 6. Immed- ...
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AD9548 SCLK SDIO SDO CS SCLK DON'T CARE SDIO DON'T CARE 16-BIT INSTRUCTION HEADER Figure 57. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data ...
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I²C SERIAL PORT OPERATION 2 The I C interface has the advantage of requiring only two control pins and facto standard throughout the I industry. However, its disadvantage is programming speed, which is 400 kbps maximum. The ...
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AD9548 The acknowledge bit (A) is the ninth bit attached to any 8-bit data byte. An acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has been received done by ...
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Data Transfer Format Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address. S Slave W A RAM address address high byte Send byte format—the send byte protocol ...
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AD9548 I/O PROGRAMMING REGISTERS The register map spans an address range from 0x0000 through 0x0E3F (0 to 3647, decimal). Each address provides access to 1 byte (eight bits) of data. Each individual register is identified by its four-digit hexadecimal address ...
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REGISTER ACCESS RESTRICTIONS Read and write access to the register map may be restricted depending on the register in question, the source and direction of access, and the current state of the device. Each register can be classified into one ...
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AD9548 REGISTER MAP Table 35. Addr Opt Name D7 0000 E SPI control Unidirec- tional 0000 Dup I2C control Unused 0001 E Reserved Unused 0002 R Reserved Silicon revision number 0003 R Device ID 0004 E Readback Unused 0005 A, ...
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Addr Opt Name D7 0210 C Ref DD new profile 0211 C Watchdog Watchdog timer (ms) [15:0] [up to 65.5 sec] timer 0212 C 0213 S DAC current DAC full-scale current [7:0] 0214 S DAC shutdown 0300 C Free running ...
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AD9548 Addr Opt Name D7 0406 S Unused 0407 S Unused 0408 S Distribution Q0 [23:0] channel 0409 S dividers 040A S 040B S Unused 040C S Q1 [23:0] 040D S 040E S 040F S Unused 0410 S Q2 [23:0] ...
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Addr Opt Name D7 060E Validation Validation timer (milliseconds) [15:0] (up to 65.5 sec) 060F 0610 Redetect Redetect timer (milliseconds) [15:0] [up to 65.5 seconds] timeout 0611 0612 Digital loop Alpha-0 linear [15:0] filter 0613 coefficients 0614 Alpha-2 exponent [1:0] ...
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AD9548 Addr Opt Name D7 0640 Validation Validation timer (milliseconds) [15:0] (up to 65.5 sec) 0641 0642 Redetect Redetect timer (milliseconds) [15:0] (up to 65.5 sec) timeout 0643 0644 Digital loop Alpha-0 linear [15:0] filter 0645 coefficients 0646 Alpha-2 exponent ...
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Addr Opt Name D7 068D Unused 068E Validation Validation timer (milliseconds) [15:0] (up to 65.5 sec) 068F 0690 Redetect Redetect timer (milliseconds) [15:0] (up to 65.5 seconds) timeout 0691 0692 Digital loop Alpha-0 linear [15:0] filter 0693 coefficients 0694 Alpha-2 ...
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AD9548 Addr Opt Name D7 06C0 Validation Validation timer (milliseconds) [15:0] (up to 65.5 sec) 06C1 06C2 Redetect Redetect timer (milliseconds) [15:0] (up to 65.5 sec) timeout 06C3 06C4 Digital loop Alpha-0 linear [15:0] filter 06C5 coefficients 06C6 Alpha-2 exponent ...
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Addr Opt Name D7 0A03 A, C ResetFunc Unused 0A04 A, C IRQ clearing Unused 0A05 A, C Unused 0A06 A, C Switching 0A07 A, C Unused 0A08 A, C Ref AA new profile 0A09 A, C Ref BB new ...
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AD9548 Addr Opt Name D7 0D0A R, C DPLL status Offset slew limiting 0D0B R, C Frequency clamped 0D0C R, C Ref A Profile selected 0D0D R, C Ref AA Profile selected 0D0E R, C Ref B Profile selected 0D0F ...
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Addr Opt Name D7 0E25 E Profile 2 and Data: 100 bytes Profile 3 0E26 E Address: 0x0680 0E27 E 0E28 E Profile 4 and Data: 100 bytes Profile 5 0E29 E Address: 0x0700 0E2A E 0E2B E Profile 6 ...
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AD9548 REGISTER MAP BIT DESCRIPTIONS SERIAL PORT CONFIGURATION (REGISTER 0000 TO REGISTER 0005) Table 36. Serial Configuration Address Bits Bit Name 0000 [7] Unidirectional [6] LSB first [5] Soft reset [4] Long instruction [0] Unused Table 37. Reserved Register Address ...
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SYSTEM CLOCK (REGISTER 0100 TO REGISTER 0108) Table 42. Charge Pump and Lock Detect Control Address Bits Bit Name 0100 [7] External loop filter enable [6] Charge pump mode [5:3] Charge pump current [2] Lock detect timer disable [1:0] Lock ...
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AD9548 Table 45. Nominal System Clock (SYSCLK) Period Address Bits Bit Name 0103 [7:0] System clock period (expressed in femtoseconds) 0104 [7:0] 0105 [7:5] Unused [4:0] System clock period 1 Units are femtoseconds. The default value is 0x0F424 = 1,000,000 ...
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Register 0209 to Register 0210—IRQ Mask The IRQ mask register bits form a one-to-one correspondence with the bits of the IRQ monitor register (Address 0D02 to Address 0D09). When set to Logic 1, the IRQ mask bits enable the corresponding ...
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AD9548 Table 53. IRQ Mask for Reference Inputs Address Bits Bit Name 020D [7] Ref AA new profile [6] Ref AA validated [5] Ref AA fault cleared [4] Ref AA fault [3] Ref A new profile [2] Ref A validated ...
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DPLL CONFIGURATION (REGISTER 0300 TO REGISTER 031B) Table 56. Free Running Frequency Tuning Word Address Bits Bit Name 0300 [7:0] Frequency (expressed as a 48-bit 0301 [7:0] frequency tuning 0302 [7:0] word) 0303 [7:0] 0304 [7:0] 0305 [7:0] 1 The ...
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AD9548 Table 61. Incremental Closed-Loop Phase Lock Offset Step Size Address Bits Bit Name 0314 [7:0] Incremental phase lock offset step size (expressed in pico- seconds per step) 0315 [7:0] 1 The default incremental closed-loop phase lock offset step size ...
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CLOCK DISTRIBUTION OUTPUT CONFIGURATION (REGISTER 0400 TO REGISTER 0419) 1 Table 65. Distribution Settings Address Bits Bit Name 0400 [7:6] Unused [5] External distribution resistor [4] Receiver mode [3] OUT3 power-down [2] OUT2 power-down [1] OUT1 power-down [0] OUT0 power-down ...
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AD9548 Table 67. Distribution Synchronization Address Bits Bit Name 0402 [7:6] Unused [5:4] Sync source [3] OUT3 sync mask [2] OUT2 sync mask [1] OUT1 sync mask [0] OUT0 sync mask Table 68. Automatic Synchronization Address Bits Bit Name 0403 ...
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Address Bits Bit Name 0405 [7:6] Unused [5] OUT1 CMOS phase invert [4] OUT1 polarity invert [3] OUT1 drive strength [2:0] OUT1 mode 0406 [7:6] Unused [5] OUT2 CMOS phase invert [4] OUT2 polarity invert [3] OUT2 drive strength [2:0] ...
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AD9548 Address Bits Bit Name 0407 [7:6] Unused [5] OUT3 CMOS phase invert [4] OUT3 polarity invert [3] OUT3 drive strength [2:0] OUT3 mode Register 0408 to Register 0417—Distribution Channel Dividers 1 Table 70. Q0 Divider Address Bits Bit Name ...
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Table 73. Q3 Divider Address Bits Bit Name 0414 [7:0] Q3 0415 [7:0] 0416 [7:0] 0417 [7:6] Unused [5: The default value is 0 (or divide by 1). REFERENCE INPUT CONFIGURATION (REGISTER 0500 TO REGISTER 0507) Table ...
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AD9548 Table 75. Reference Logic Family Address Bits Bit Name 0501 [7:6] Ref BB logic family [5:4] Ref B logic family [3:2] Ref AA logic family [1:0] Ref A logic family 0502 [7:6] Ref DD logic family [5:4] Ref D ...
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Table 77. Phase Build-Out Switching Address Bits Bit Name 0507 [7:3] Unused [2:0] Phase master threshold priority PROFILE REGISTERS (REGISTER 0600 TO REGISTER 07FF) Note that the default value of every bit is 0 for Profile 0 to Profile 7. ...
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AD9548 Table 83. Digital Loop Filter Coefficients—Profile 0 Address Bits Bit Name 0612 [7:0] Alpha-0 linear 0613 [7:0] 0614 [7:6] Alpha-2 exponent [5:0] Alpha-1 exponent 0615 [7:1] Beta-0 linear [0] Alpha-2 exponent 0616 [7:0] Beta-0 linear 0617 [7] Unused [6:2] ...
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Table 86. Fractional Feedback Divider—Profile 0 Address Bits Bit Name 0626 [7:0] V 0627 [7:4] U [3:2] Unused [1:0] V 0628 [7:6] Unused [5:0] U Table 87. Lock Detectors—Profile 0 Address Bits Bit Name 0629 [7:0] Phase lock threshold (units ...
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AD9548 Table 90. Tolerance—Profile 1 Address Bits Bit Name 063A [7:0] Inner tolerance 063B [7:0] 063C [7:4] Unused [3:0] Inner tolerance 063D [7:0] Outer tolerance 063E [7:0] 063F [7:4] Unused [3:0] Outer tolerance Table 91. Validation Timer—Profile 1 Address Bits ...
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Table 94. R-Divider—Profile 1 Address Bits Bit Name 0650 [7:0] R 0651 [7:0] 0652 [7:0] 0653 [7:6] Unused [5: The value stored in the R-divider register yields an actual divide ratio of one more than the programmed ...
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AD9548 Table 99. Reference Period—Profile 2 Address Bits Bit Name 0681 [7:0] Reference period (in femtoseconds) 0682 [7:0] 0683 [7:0] 0684 [7:0] 0685 [7:0] 0686 [7:0] 0687 [7:2] Unused [1:0] Reference period Table 100. Tolerance—Profile 2 Address Bits Bit Name ...
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Address Bits Bit Name 069C [7] Delta-1 exponent [6:0] Delta-0 linear 069D [7:4] Alpha-3 exponent [3:0] Delta-1 exponent 1 The digital loop filter coefficients (α, β, γ, and δ) have the general form: x(2 The value of the linear component ...
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AD9548 Register 06B2 to Register 07FF—Profile 3 Table 108. Priorities—Profile 3 Address Bits Bit Name 06B2 [7] Phase lock scale [6] Unused [5:3] Promoted priority [2:0] Selection priority Table 109. Reference Period—Profile 3 Address Bits Bit Name 06B3 [7:0] Reference ...
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Address Bits Bit Name 06C9 [7] Unused [6:2] Beta-1 exponent [1:0] Beta-0 linear 06CA [7:0] Gamma-0 linear 06CB [7:0] 06CC [7:6] Unused [5:1] Gamma-1 exponent [0] Gamma-0 linear 06CD [7:0] Delta-0 linear 06CE [7] Delta-1 exponent [6:0] Delta-0 linear 06CF ...
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AD9548 Table 117. Lock Detectors—Profile 3 Address Bits Bit Name 06DB [7:0] Phase lock threshold (units determined by 06DC [7:0] Register 0x06B2[7]) 06DD [7:0] Phase lock fill rate 06DE [7:0] Phase lock drain rate 06DF [7:0] Frequency lock thresh-old (in ...
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Table 119. Loop Mode Address Bits Bit Name 0A01 [7] Unused [6] User holdover [5] User freerun [4:3] User selection mode [2:0] User reference selection Table 120. Cal/Sync Address Bits Bit Name 0A02 [7:2] unused [1] Sync distribution [0] Calibrate ...
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AD9548 Register 0A03—ResetFunc 1 Table 121. Reset Functions Address Bits Bit Name 0A03 [7] Unused [6] Clear LF [5] Clear CCI [4] Clear phase accumulator [3] Reset auto sync [2] Reset TW history [1] Reset all IRQs [0] Reset watchdog ...
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Table 125. IRQ Clearing for History Update, Frequency Limit, and Phase Slew Limit Address Bits Bit Name 0A07 [7:5] Unused [4] History updated [3] Frequency unclamped [2] Frequency clamped [1] Phase slew unlimited [0] Phase slew limited Table 126. IRQ ...
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AD9548 Table 127. Incremental Phase Offset Control Address Bits Bit Name 0A0C [7:3] Unused [2] Reset phase offset [1] Decr phase offset [0] Incr phase offset Table 128. Reference Profile Selection State Machine Startup Address Bits Bit Name 0A0D [7] ...
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Address Bits Bit Name 0A0F [7] Ref Mon Override DD [6] Ref Mon Override D [5] Ref Mon Override CC [4] Ref Mon Override C [3] Ref Mon Override BB [2] Ref Mon Override B [1] Ref Mon Override AA ...
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AD9548 Register 0D02 to Register 0D09—IRQ Monitor If not masked via the IRQ mask register (Address 0209 to Address 0210), then the appropriate IRQ monitor bit is set to a Logic 1 when the indicated event occurs. These bits can ...
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Address Bits Bit Name 0D07 [7] Ref BB new profile [6] Ref BB validated [5] Ref BB fault cleared [4] Ref BB fault [3] Ref B new profile [2] Ref B validated [1] Ref B fault cleared [0] Ref B ...
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AD9548 Table 138. Input Reference Status Address Bits Bit Name 0D0C [7] Profile selected [6:4] Selected profile [3] Valid [2] Fault [1] Fast [0] Slow 0D0D [7:0] 0D0E [7:0] 0D0F [7:0] 0D10 [7:0] 0D11 [7:0] 0D12 [7:0] 0D13 [7:0] 1 ...
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EEPROM STORAGE SEQUENCE (REGISTER 0E10 TO REGISTER 0E3F) The default settings of Register 0E10 to Register 0E33 embody a sample scratch pad instruction sequence. The following is a description of the register defaults under the assumption that the controller has ...
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AD9548 Table 145. EEPROM Storage Sequence for Clock Distribution Settings Address Bits Bit Name 0E1B [7:0] Clock distribution 0E1C [7:0] Clock distribution 0E1D [7:0] 0E1E [7:0] I/O update Table 146. EEPROM Storage Sequence for Reference Input Settings Address Bits Bit ...
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Table 148. EEPROM Storage Sequence for Profile 2 and Profile 3 Settings Address Bits Bit Name 0E25 [7:0] Profile 2 and Profile 3 0E26 [7:0] Profile 2 and Profile 3 0E27 [7:0] Table 149. EEPROM Storage Sequence for Profile 4 ...
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AD9548 Table 151. EEPROM Storage Sequence for Operational Control Settings Address Bits Bit Name 0E2F [7:0] Operational controls 0E30 [7:0] Operational controls 0E31 [7:0] 0E32 [7:0] I/O update Table 152. EEPROM Storage Sequence for End of Data Address Bits Bit ...
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POWER SUPPLY PARTITIONS The AD9548 features multiple power supplies, and their power consumption varies with the AD9548 configuration. This section provides information about which power supplies can be grouped together and how the power consumption of each block varies with ...
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AD9548 THERMAL PERFORMANCE Table 154. Thermal Parameters for the AD9548 88-Lead LFCSP Package Symbol Thermal Characteristic Using a JEDEC51-7 Plus JEDEC51-5 2S2P Test Board θ Junction-to-ambient thermal resistance, 0.0 m/s airflow per JEDEC JESD51-2 (still air) JA θ Junction-to-ambient thermal ...
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CALCULATING DIGITAL FILTER COEFFICIENTS The digital loop filter coefficients ( , , , and (see Figure 40)) relate to the time constants ( and equivalent analog circuit for a third order loop filter (Figure ...
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AD9548 integer, then Otherwise the nearest integer to x. For example, round(2. round(2. and round(−3.1) = −3. The ceil() function y = ceil( ...
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This leads to the following quantized value, which is very close −5 to the desired value of 6.98672x10 : 019 986688823 quantized CALCULATION OF THE REGISTER VALUES The quantized coefficient consists of two components, ...
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... MAX 0.90 0.85 0.80 0.30 SEATING PLANE 0.23 0.18 ORDERING GUIDE 1 Model Temperature Range AD9548BCPZ −40°C to +85°C AD9548BCPZ-REEL7 −40°C to +85°C AD9548/PCBZ −40°C to +85° RoHS Compliant Part. 0.60 MAX 11.75 0.50 BSC SQ BSC 0.50 0.40 0.30 ...
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NOTES Rev Page 111 of 112 AD9548 ...
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AD9548 NOTES ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08022-0-10/10(A) Rev Page 112 of 112 ...