IDTCV115-2PV IDT, Integrated Device Technology Inc, IDTCV115-2PV Datasheet - Page 13

• Manufacturer Part Number: IDTCV115-2PV
• Description: IC FLEXPC CLK PROGR P4 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: FlexPC™r
• Type: PC Clockr

Specifications of IDTCV115-2PV

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: CV115-2PV

ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
NOTES:
1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
2. This parameter is guaranteed by design, but not 100% production tested.
3. See TIMING DIAGRAMS for timing requirements.
IDTCV115-2
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
Symbol
I
I
V
V
DD3.3OP
DD3.3PD
T
C
C
IH
IL
L
C
V
V
STAB
I
F
OUT
PIN
_FS
INX
_FS
IL
IH
IL
IN
I
Input HIGH Voltage
Input LOW Voltage
FS Input HIGH Voltage
FS Input LOW Voltage
Input LeakageCurrent
Operating Supply Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
Clock Stabilization
Modulation Frequency
T
T
T
T
T
T
T
DRIVE
FALL
RISE
DRIVE
DRIVE
FALL
RISE
_PD#
_PD#
_CPU_Stop#
_CPU_Stop#
_SRC
_PD#
_CPU_Stop#
A
= 0°C to +70°C, Supply Voltage: V
(3)
(2)
Parameter
(2)
(2)
(2)
(1)
(2)
(2,3)
(3)
(2)
(2)
(2)
For FSA.B.C and Test_Mode
3.3V ± 5%
3.3V ± 5%
0< V
Full active, C
All differential pairs driven
All differential pairs tri-stated
V
Logic inputs
Output pin capacitance
X1 and X2 pins
From V
Triangular modulation
SRC output enable after PCI_Stop# de-assertion
CPU output enable after PD# de-assertion
Fall time of PD#
Rise time of PD#
CPU output enable after CPU_Stop# de-assertion
Fall time of PD#
Rise time of PD#
For FSA.B.C and Test_Mode
DD
IN
= 3.3V
< V
DD
DD
DD
power-up or de-assertion of PD# to first clock
, no internal pull-up or pull-down
= 3.3V ± 5%
L
= full load
Test Conditions
13
COMMERCIAL TEMPERATURE RANGE
V
V
SS
SS
Min.
0.7
–5
—
—
—
—
—
—
—
—
—
30
—
—
—
—
—
—
—
2
- 0.3
- 0.3
14.31818
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V
V
DD
DD
Max.
0.35
400
300
0.8
1.8
+5
70
12
—
33
15
10
7
5
6
5
5
5
5
5
+ 0.3
+ 0.3
MHz
Unit
KHz
mA
mA
mA
nH
ms
pF
ns
us
ns
ns
us
ns
ns
V
V
V
V