ICS9161A-01CW16T IDT, Integrated Device Technology Inc, ICS9161A-01CW16T Datasheet

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ICS9161A-01CW16T

Manufacturer Part Number
ICS9161A-01CW16T
Description
IC FREQUENCY GENERATOR 16-SOIC
Manufacturer
IDT, Integrated Device Technology Inc
Type
Frequency Generatorr
Datasheet

Specifications of ICS9161A-01CW16T

Input
Clock, Crystal
Output
Clock
Frequency - Max
120MHz
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
16-SOIC
Frequency-max
120MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
9161A-01CW16T
General Description
The ICS9161A is a fully programmable graphics clock
generator. It can generate user-specified clock
frequencies using an externally generated input
reference or a single crystal. The output frequency is
programmed by entering a 24-bit digital word through
the serial port. Two fully user-programmable phase-
locked loops are offered in a single package. One PLL
is designed to drive the memory clock, while the
second drives the video clock. The outputs may be
changed on-the-fly to any desired frequency between
390 kHz and 120 MHz. The ICS9161A is ideally suited
for any design where multiple or varying frequencies
are required.
This part is ideal for graphics applications. It generates
low jitter, high speed pixel clocks. It can be used to replace
multiple, expensive high speed crystal oscillators. The
flexibility of the device allows it to generate non-standard
graphics clocks.
The ICS9161A is also ideal in disk drives. It can generate
zone clocks for constant density recording schemes. The low
profile, 16-pin SOIC or PDIP package and low jitter outputs
are especially attractive in board space critical disk drives.
The leader in the area of multiple output clocks on a single
chip, ICS has been shipping graphics frequency generators
since October, 1990, and is constantly improving the
phase-locked loop. The ICS9161A incorporates a patented
fourth generation PLL that offers the best jitter performance
available.
Block Diagram
0210I—03/21/05
Dual Programmable Graphics Frequency Generator
SEL1-DATA
SEL0-CLK
PD
INIT1
INIT2
9161
X1
X2
XTAL
OSC
24
24
Integrated
Circuit
Systems, Inc.
DECODE
LOGIC
ADDRESS
DATA
3
21
REGISTERS
CONTROL REG
POR
ROM
INIT
21
21
21
3-TO-1
MUX
(D0-D20)
(D0-D20)
MCLK
VCLK
21
21
Features
Pin-for-pin and function compatible with ICD2061A
Dual programmable graphics clock generator
Memory and video clocks are individually
programmable on-the-fly
Ideal for designs where multiple or varying
frequencies are required
Increased frequency resolution from optional pre-
divide by 2 on the M counter
Output enable feature available for tristating outputs
Independent clock outputs range from 390 kHz to
120 MHz for VDD >4.75V
Power-down capabilities
Low power, high speed 0.8µ CMOS technology
Glitch-free transitions
Available in 16-pin, 300-mil SOIC or PDIP package
f
REF
D14-D20
D14-D20
D4-D10
DIVIDE
DIVIDE
DIVIDE
(M÷)
VCO
REF
(N÷)
(M÷)
REF
7
7
7
P= 2 or 4
Pscale
D4-D10
DIVIDE
VCO
(N÷)
VCO
7
D0-D3
D0-D3
4
VCO
Pscale
P= 2
4
VCO OUTPUT
R=1,2,4,8,16
32,64,128
D11-D13
DIVIDER
VCO OUTPUT
3
R=1,2,4,8,16
32,64,128
D11-D13
DIVIDER
EXTCLK
3
ICS9161A
MUX
EXTSEL
OUTPUT
DRIVER
CMOS
OUTPUT
DRIVER
CMOS
VCLK
OE
MCLK

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ICS9161A-01CW16T Summary of contents

Page 1

... The flexibility of the device allows it to generate non-standard graphics clocks. The ICS9161A is also ideal in disk drives. It can generate zone clocks for constant density recording schemes. The low profile, 16-pin SOIC or PDIP package and low jitter outputs are especially attractive in board space critical disk drives ...

Page 2

... Pin Descriptions 0210I—03/21/05 Pin Configuration 16-Pin 300- mil SOIC or PDIP ICS9161A ...

Page 3

... The ICS9161A places the three video clock registers and the memory clock register in a known state upon power- up. The registers are initialized based on the state of the INIT1 and INIT0 pins at application of power to the device. The INIT pins must ramp up with VDD if a logical 1 on either pin is required ...

Page 4

... Control Register Definitions The control register allows the user to adjust various internal options. The register is defined as follows 0210I—03/21/ ICS9161A ...

Page 5

... The pins SEL0 and SEL1 perform the dual functions of select-ing registers and serial programming. In serial programming mode, SEL0 acts as a clock pin while SEL1 acts as the data pin. The ICS9161A-01 may not be serially programmed when in power-down mode. In order to program a particular register, an unlocking sequence must occur ...

Page 6

... DD Unlike the ICD2061A, the ICS9161A’s VCO does not F =Input Reference REF require tuning to place it in certain ranges. The ICS9161A’s Frequency VCO will operate from 50 MHz to 120 MHz without M=Reference divide 3 to 129 adjusting the VCO gain. However, to maintain compatibility, the I bits are programmed as in the ICD2061A ...

Page 7

... Power Management Issues Power-down mode 1 The ICS9161A contains a mechanism to reduce the quiescent power when stand-by operation is desired. Power-down mode 1 is invoked by polling PD# low and having the proper CNTL register bit set to zero. In this mode, VCOs are shut down, the VCLK output is forced high, and the MCLK output is set to a user-defined low frequency value to refresh dynamic RAM ...

Page 8

... Electrical Characteristics at 5.0V = +5V ± 5%, 0°C ≤ AMBIENT Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 0210I—03/21/05 ) ..............0°C to 70°C OPER ) ............+260°C SOL ≤ +70° ICS9161A µ A µ A µ µ ...

Page 9

... For reference frequencies other than 14.81818 MHz, the pre-loaded ROM frequencies will shift proportionally. 3. Duty cycle is measured at CMOS threshold levels volts the interval is too short, see the time-out interval section in the control register definition. 0210I—03/21/05 (continued • ICS9161A =2.5 volts. TH ...

Page 10

... Rise and Fall Times Tristated Timing 10 ICS9161A ...

Page 11

... MCLK and Active VCLK Register Programming Timing 0210I—03/21/05 Selection Timing 11 ICS9161A ...

Page 12

... Soft Power-Down Timing (Mode 2) 0210I—03/21/05 Serial Programming Timing 12 ICS9161A ...

Page 13

... RC termination should be used on all over 50MHz outputs. 3) Optional crystal load capacitors are recommended. Capacitor Values: C1 Crystal load values determined by user C3 : 100pF ceramic All unmarked capacitors are 0.01µF ceramic Connections to VDD: 0210I—03/21/05 13 ICS9161A ...

Page 14

... Lead Count & Package Width Lead Count= digits W=.3” SOIC or .6” DIP; None=Standard Width Package Type N=DIP (Plastic) Pattern Number ( digit number for parts with ROM code patterns, if applicable) Device Type (consists digit numbers) Prefix ICS, AV=Standard Device 14 ICS9161A ...

Page 15

... Annealed Lead Free (Optional) Lead Count & Package Width Lead Count= digits W=.3” SOIC or .6” DIP; None=Standard Width Package Type M=SOIC Pattern Number ( digit number for parts with ROM code patterns, if applicable) Device Type (consists digit numbers) Prefix ICS, AV=Standard Device 15 ICS9161A ...

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