ICS93V857BG-025LF IDT, Integrated Device Technology Inc, ICS93V857BG-025LF Datasheet

IC CLOCK DRIVER 2.5V 48-TSSOP

ICS93V857BG-025LF

Manufacturer Part Number
ICS93V857BG-025LF
Description
IC CLOCK DRIVER 2.5V 48-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of ICS93V857BG-025LF

Input
Clock
Output
Clock
Frequency - Max
233MHz
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Frequency-max
233MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
93V857BG-025LF
Recommended Application:
Product Description/Features:
Switching Characteristics:
Functionality
0693M—02/19/09
2.5V Wide Range Frequency Clock Driver (33MHz - 233MHz)
A
n (
n (
n (
n (
n (
G
G
2
2
2
2
2
V
5 .
5 .
5 .
5 .
5 .
o
o
o
o
o
N
N
D
m
m
m
m
m
D
D
V
V
V
V
V
D
)
)
)
)
)
DDR Memory Modules / Zero Delay Board Fan Out
Provides complete DDR DIMM logic solution with
ICSSSTV16857, ICSSSTV16859 or ICSSSTV32852
Low skew, low jitter PLL clock driver
1 to 10 differential clock distribution (SSTL_2)
Feedback pins for input to output synchronization
PD# for power management
Spread Spectrum tolerant inputs
Auto PD when input signal removed
Choice of static phase offset available,
for easy board tuning;
-XXX = device pattern number for options listed
below.
Period jitter (>66MHz): <40ps
CYCLE - CYCLE jitter (66MHz): <120ps
CYCLE - CYCLE jitter (>100MHz): <65ps
OUTPUT - OUTPUT skew: <60ps
Output Rise and Fall Time: 650ps - 950ps
DUTY CYCLE: 49.5% - 50.5%
P
H
H
H
H
X
D
L
L
- ICS93V857-025 ...... 0ps
- ICS93V857-125 +125ps
- ICS93V857-130 .. +40ps
#
N I
C
L
P
K
U
H
H
H
L
L
L
_
T
N I
<
S
2
T
0
M
H
C
) z
L
(
) 1
K
H
L
H
L
H
L
_
N I
C
C
L
H
Z
Z
H
Z
L
L
K
T
C
L
H
Z
Z
H
Z
L
L
K
C
O
F
U
B
T
_
P
O
H
Z
Z
H
Z
L
L
U
U
T
T
S
T
F
B
_
O
H
L
Z
Z
H
L
Z
U
T
C
B
B
P
y
y
p
p
L
a
a
L
s s
s s
o
o
o
o
o
S
f f
f f
n
n
f f
e
e
a t
d
d
e t
o /
o /
1
f f
f f
4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)
Block Diagram
CLK_INC
CLK_INT
6.10 mm. Body, 0.50 mm. pitch = TSSOP
CLK_INC
CLK_INT
FB_INC
FB_INT
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
AGND
AVDD
PD#
GND
GND
GND
GND
GND
VDD
VDD
VDD
VDD
VDD
48-Pin TSSOP & TVSOP
Pin Configuration
10
12
13
14
15
16
17
18
19
20
21
22
23
24
11
1
2
3
4
5
6
7
8
9
Control
Logic
PLL
ICS93V857-XXX
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
GND
CLKC7
CLKT7
VDD
PD#
FB_INT
FB_INC
VDD
FB_OUTC
FB_OUTT
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9

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ICS93V857BG-025LF Summary of contents

Page 1

Wide Range Frequency Clock Driver (33MHz - 233MHz) Recommended Application: • DDR Memory Modules / Zero Delay Board Fan Out • Provides complete DDR DIMM logic solution with ICSSSTV16857, ICSSSTV16859 or ICSSSTV32852 Product Description/Features: • Low skew, low jitter ...

Page 2

ICS93V857-XXX Pin Descriptions ...

Page 3

Absolute Maximum Ratings Supply Voltage (VDD & AVDD -0.5V to 4.6V Logic Inputs . . . . . . . . . . . . . . . . ...

Page 4

ICS93V857-XXX Recommended Operating Condition (see note1 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) A PARAMETER SYMBOL Supply Voltage V DDQ Low level input voltage High level input voltage V DC ...

Page 5

Timing Requirements 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) A PARAMETER SYMBOL 3 Max clock frequency Application Frequency 3 Range Input clock duty cycle CLK stabilization Switching Characteristics PARAMETER SYMBOL ...

Page 6

ICS93V857-XXX VDD/2 ICS93V857 -VDD/2 NOTE: V (TT) = GND Y , FB_OUTC FB_OUTT X 0693M—02/19/09 Parameter Measurement Information (CLKC) ICS93V857 GND Figure 1. IBIS Model Output Load -VDD ...

Page 7

CLK_INC CLK_INT FB_INC FB_INT FB_OUTC FB_OUTT FB_OUTC FB_OUTT FB_OUTC FB_OUTT X 0693M—02/19/09 Parameter Measurement Information ...

Page 8

ICS93V857-XXX Y , FB_OUTC FB_OUTT X 20% Clock Inputs and Outputs 0693M—02/19/09 Parameter Measurement Information t jit(hper_n) t jit(hper_n+ jit(hper) jit(hper_n) 2xf O Figure 7. Half-Period Jitter 80% t ...

Page 9

INDEX INDEX AREA AREA aaa 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) Ordering Information 93V857yG-025LFT 93V857yG-125LFT 93V857yG-130LFT Example: XXXX PPP ...

Page 10

ICS93V857-XXX INDEX INDEX AREA AREA 4.40 mm. Body, 0.40 mm. pitch TSSOP (16 mil) (173 mil) Ordering Information 93V857yL-025LFT 93V857yL-125LFT 93V857yL-130LFT Example: XXXX PPP ...

Page 11

DIMENSIONS SYMBOL MIN 0.18 e Ordering Information 93V857yK-025LFT 93V857yK-125LFT 93V857yK-130LFT Example: XXXX PPP LF T 0693M—02/19/09 THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE MAX. 0.8 1.0 0 ...

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