ICS9FG1904BK-1LF IDT, Integrated Device Technology Inc, ICS9FG1904BK-1LF Datasheet
ICS9FG1904BK-1LF
Specifications of ICS9FG1904BK-1LF
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ICS9FG1904BK-1LF Summary of contents
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Integrated Circuit Systems, Inc. Frequency Generator for CPU, PCIe Gen 1, PCIe Gen 2 & FBD Recommended Application: DB1900GS/GSO with 15:4 output grouping Features: • Power up default is all outputs in 1:1 mode • DIF_(14:0) can be “gear-shifted” from ...
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Integrated Circuit Systems, Inc. Pin Description PIN # PIN NAME PIN TYPE 1 IREF OUT 2 GNDA PWR 3 VDDA PWR 4 HIGH_BW# 5 FS_A_410 6 DIF_0 OUT 7 DIF_0# OUT 8 DIF_1 OUT 9 DIF_1# OUT 10 GND PWR ...
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Integrated Circuit Systems, Inc. Pin Description (Continued) PIN # PIN NAME PIN TYPE 37 OE9 DIF_9 OUT 39 DIF_9# OUT 40 OE10 DIF_10 OUT 42 DIF_10# OUT 43 OE11 DIF_11 OUT 45 DIF_11# OUT ...
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Integrated Circuit Systems, Inc. General Description ThThe ICS9FG1904-1 follows the Intel DB1900GS Differential Buffer Specification, except for the output groupings and gear table. The gear table is a blend of the GS and GSO gearing. This buffer provides 19 output ...
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Integrated Circuit Systems, Inc. ICS 9FG1904B-1 Programmable Gear Ratios CLK_IN Geared DIF (CPU FSB) Outputs M MHz MHz 100.00 133.33 3 100.00 166.67 3 100.00 200.00 1 100.00 266.67 3 100.00 333. 100.00 400.00 1 133.33 166.67 4 ...
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Integrated Circuit Systems, Inc. ICS 9FG1904B-1 1:1 PLL Programming Byte 9, Byte9, Byte 9, bit 2 bit 1 bit 0 FSC FSB FS_A_410 Notes:FS_A_410 ...
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Integrated Circuit Systems, Inc. Absolute Max PARAMETER SYMBOL 3.3V Core Supply Voltage VDD_A 3.3V Logic Supply Voltage VDD_In Storage Temperature Ts Ambient Operating Temp Tambient Case Temperature Tcase Input ESD protection ESD prot Electrical Characteristics - Input/Supply/Common Output Parameters T ...
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Integrated Circuit Systems, Inc. Electrical Characteristics - DIF 0.7V Current Mode Differential Pair 70° 3.3 V +/-5%; C =2pF PARAMETER SYMBOL Current Source Output 1 Zo Impedance Voltage High VHigh ...
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Integrated Circuit Systems, Inc. Electrical Characteristics - Skew and Differential Jitter Parameters 70°C; Supply Voltage V = 3.3 V +/- Group Parameter Input-to-Output Skew in PLL mode (1:1 only), t CLK_IN, DIF[x:0] SPO_PLL nominal ...
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Integrated Circuit Systems, Inc. Programming the 9FG1904B-1 The 9FG1904B-1 uses advanced power saving features to detect when only geared outputs or only 1:1 outputs are needed. It then shuts down the unused PLL. At power up all outputs are coming ...
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Integrated Circuit Systems, Inc. GS Gear Ratios CLK_IN Geared DIF (CPU FSB) Outputs MHz MHz 100.00 133. 100.00 166. 100.00 200. 100.00 266. 100.00 333.33 ...
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Integrated Circuit Systems, Inc. Using M/N Programming to Obtain Other Gear Ratios M/N programming can be used to obtain input output frequency combinations that are not preconfigured in the 9FG1904B-1. Refer to Figure 2 PLL Block Diagram. The internal architecture ...
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Integrated Circuit Systems, Inc. when using CK410/CK410B, 9FG1200, and SMB_A(2:0) = 000 SMB Adr: D0 9FG1904-1 (DB1900GS) SMB_A(2:0) = 001 SMB Adr: D2 9FG1904-1 (DB1900GS) SMB_A(2:0) = 010 SMB Adr: D4 9FG1904-1 (DB1900GS) SMB_A(2:0) = 011 SMB Adr: D6 9FG1904-1 ...
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Integrated Circuit Systems, Inc. General SMBus serial interface information for the ICS9FG1904B-1 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address *D0 • ICS clock will acknowledge • Controller (host) sends the ...
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Integrated Circuit Systems, Inc. SMBusTable: Gear Ratio Select Register Byte 0 Pin # Name Bit 7 DIF(14:0) Group of 15 gear ratio enable DIF(18:15) Group of 4 gear ratio enable Bit 6 - Bit 5 - Gear Ratio FS4 (Inverse ...
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Integrated Circuit Systems, Inc. SMBusTable: Output Enable Readback Register Byte 4 Pin # Name Bit 7 69 Readback - OE17_18# Input Bit 6 60 Readback - OE15_16# Input Bit 5 Bit 4 54 Bit Bit 2 Bit ...
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Integrated Circuit Systems, Inc. SMBusTable: Control Pin Readback Register Byte 8 Pin # Name 5 Bit 7 Bit 6 Bit 5 Bit 4 DIF_18 Bit 3 DIF_17 Bit 2 DIF_16 DIF_15 Bit 1 DIF_14 Bit 0 SMBusTable: 1:1 PLL Operating ...
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Integrated Circuit Systems, Inc. SMBus Table: Gear PLL Frequency Control Register Byte 12 Pin # Name Bit 7 - Gear PLL N Div7 Bit 6 - Gear PLL N Div6 - Gear PLL N Div5 Bit 5 Bit 4 - ...
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Integrated Circuit Systems, Inc. SMBusTable: Reserved Register Byte 16 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus Table: 1:1 PLL Frequency Control Register Byte 17 Pin # Name ...
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Integrated Circuit Systems, Inc. SMBusTable: Reserved Register Byte 20 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBusTable: Test Byte Register Byte 21 Test ` Bit 7 Bit 6 ...
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Integrated Circuit Systems, Inc. Index Area Top View D Chamfer 4x 0.6 x 0.6 max OPTIONAL DIMENSIONS SYMBOL MIN 0.25 Reference b 0.18 e 0.50 BASIC Ordering Information ICS 9FG1904BK-1LFT Example: ICS ...
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Integrated Circuit Systems, Inc. Revision History Rev. Issue Date Description 1. Added Output Divider Table. 2. Added Phase Jitter Table to electrical characteristics. A 05/04/07 3. Added M/N programming information. 4. Changed part number to reference 9FG1904B-1. B 08/03/07 Release ...