W256H Cypress Semiconductor Corp, W256H Datasheet

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W256H

Manufacturer Part Number
W256H
Description
IC CLK BUFF 12OUT SDRAM 28SSOP
Manufacturer
Cypress Semiconductor Corp
Type
Fanout Buffer (Distribution)r
Datasheet

Specifications of W256H

Number Of Circuits
1
Ratio - Input:output
1:12
Differential - Input:output
No/No
Input
DDR, SDRAM
Output
DDR, SDRAM
Frequency - Max
180MHz
Voltage - Supply
2.375 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
28-SSOP
Frequency-max
180MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1399

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Cypress Semiconductor Corporation
Document #: 38-07256 Rev. *C
Features
Note:
1. Internal 100K pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH.
• One input to 12 output buffer/drivers
• Supports up to 2 DDR DIMMs or 3 SDRAM DIMMS
• One additional output for feedback
• SMBus interface for individual output control
• Low skew outputs (< 100 ps)
• Supports 266 MHz and 333 MHz DDR SDRAM
• Dedicated pin for power management support
• Space-saving 28-pin SSOP package
SCLOCK
PWR_DWN#
Block Diagram
SEL_DDR
BUF_IN
SDATA
Powerdown
Decoding
Control
VDD3.5_2.5
SMBus
12 Output Buffer for 2 DDR and 3 SRAM DIMMS
&
3901 North First Street
DDR5T_SDRAM10
DDR4C_SDRAM9
DDR5C_SDRAM11
FBOUT
DDR0T_SDRAM0
DDR0C_SDRAM1
DDR1T_SDRAM2
DDR1C_SDRAM3
DDR2T_SDRAM4
DDR2C_SDRAM5
DDR3T_SDRAM6
DDR3C_SDRAM7
DDR4T_SDRAM8
Functional Description
The W256 is a 3.3V/2.5V buffer designed to distribute
high-speed clocks in PC applications. The part has 12 outputs.
Designers can configure these outputs to support 3 unbuffered
standard SDRAM DIMMs and 2 DDR DIMMs. The W256 can
be used in conjunction with the W250-02 or similar clock
synthesizer for the VIA Pro 266 chipset.
The W256 also includes an SMBus interface which can enable
or disable each output clock. On power-up, all output clocks
are enabled (internal pull-up).
DDR0C_SDRAM1
DDR1C_SDRAM3
DDR2C_SDRAM5
DDR0T_SDRAM0
DDR1T_SDRAM2
DDR2T_SDRAM4
*PWR_DWN#
VDD3.3_2.5
VDD3.3_2.5
VDD3.3_2.5
San Jose
BUF_IN
FBOUT
GND
GND
Pin Configuration
,
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CA 95134
Top View
SSOP
Revised August 30, 2004
28
27
26
25
24
23
22
21
20
19
18
17
16
15
[1]
SEL_DDR*
DDR5T_SDRAM10
DDR5C_SDRAM11
VDD3.3_2.5
GND
DDR4T_SDRAM8
DDR4C_SDRAM9
VDD3.3_2.5
GND
DDR3T_SDRAM6
DDR3C_SDRAM7
GND
SCLK
SDATA
408-943-2600
W256

Related parts for W256H

W256H Summary of contents

Page 1

... PWR_DWN# SEL_DDR Note: 1. Internal 100K pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH. Cypress Semiconductor Corporation Document #: 38-07256 Rev. *C Functional Description The W256 is a 3.3V/2.5V buffer designed to distribute high-speed clocks in PC applications. The part has 12 outputs. ...

Page 2

Pin Summary Name Pins SEL_DDR 28 SCLK 16 SDATA 15 BUF_IN 10 FBOUT 1 PWR_DWN# 2 DDR[0:5]T_SDRAM 3, 7, 12, 19, 23, 27 [0,2,4,6,8,10] DDR[0:5]C_SDRAM 4, 8, 13, 18, 22, 26 [1,3,5,7,9, 11] VDD3.3_2 14, 21, 25 GND ...

Page 3

Serial Configuration Map • The Serial bits will be read by the clock driver in the following order: Byte 0 — Bits Byte 1 — Bits ...

Page 4

Maximum Ratings Supply Voltage to Ground Potential ..................–0.5 to +7.0V DC Input Voltage (except BUF_IN) ............ –0. Storage Temperature .................................. –65°C to +150°C Static Discharge Voltage ............................................>2000V (per MIL-STD-883, Method 3015) [2] Operating Conditions Parameter V Supply Voltage ...

Page 5

Switching Characteristics Parameter Name – Operating Frequency ÷ t [4,5] – Duty Cycle = SDRAM Rising Edge Rate 3 t SDRAM Falling Edge Rate 4 t DDR Rising Edge Rate 3d t DDR Falling Edge ...

Page 6

Switching Waveforms (continued) SDRAM Buffer HH and LL Propagation Delay 1.5V INPUT 1.5V OUTPUT t 6 Figure 1 shows the differential clock directly terminated by a 120 Ω resistor Device Out Under Test Out Figure 1. Differential ...

Page 7

... Cermaic Caps C1 = 10–22 µ VIA to GND plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors All bypass caps = 0.1 µF ceramic Ordering Information Ordering Code W256H W256HT Lead Free CYW256OXC CYW256OXCT Document #: 38-07256 Rev VDD 10 µF 0.005 µ ...

Page 8

... Document #: 38-07256 Rev. *C © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 9

Document History Page Document Title: W256 12 Output Buffer for 2 DDR and 3 SRAM DIMMS Document Number: 38-07256 REV. ECN NO. Issue Date ** 110521 12/04/01 *A 112153 03/01/02 *B 122858 12/19/02 *C 258671 See ECN Document #: 38-07256 ...

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