CY22150KFZXC Cypress Semiconductor Corp, CY22150KFZXC Datasheet

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CY22150KFZXC

Manufacturer Part Number
CY22150KFZXC
Description
IC CLOCK GEN PROG FLASH 16-TSSOP
Manufacturer
Cypress Semiconductor Corp
Type
Clock Generator, Fanout Distributionr
Datasheets

Specifications of CY22150KFZXC

Number Of Circuits
1
Package / Case
16-TSSOP
Pll
Yes
Input
Crystal
Output
Clock
Ratio - Input:output
1:6
Differential - Input:output
No/No
Frequency - Max
200MHz
Divider/multiplier
Yes/No
Voltage - Supply
2.375 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Frequency-max
200MHz
Maximum Input Frequency
133 MHz
Minimum Input Frequency
1 MHz
Output Frequency Range
0.08 MHz to 200 MHz
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Number Of Elements
1
Supply Current
45mA
Pll Input Freq (min)
1MHz
Pll Input Freq (max)
133MHz
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 70C
Package Type
TSSOP
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.465V
Operating Temperature Classification
Commercial
Pin Count
16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY30700 - KIT PROG FOR CY22150
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Features
Benefits
Cypress Semiconductor Corporation
Document #: 38-07104 Rev. *I
Part Number
Integrated phase-locked loop (PLL)
Commercial and industrial operation
Flash programmable
Field programmable
Two-wire serial programming interface
Low skew, low jitter, high accuracy outputs
3.3V operation with 2.5V output option
16-pin TSSOP
Internal PLL to generate six outputs up to 200 MHz. Able to
generate custom frequencies from an external crystal or
a driven source.
Performance guaranteed for applications that require an
extended temperature range.
CY22150FC
CY22150FI
Logic Block Diagram
Outputs
Serial
Programming
Interface
6
6
8 MHz to 30 MHz (external crystal)
1 MHz to 133 MHz (driven clock)
8 MHz to 30 MHz (external crystal)
1 MHz to 133 MHz (driven clock)
XOUT
XIN
SDAT
SCLK
Input Frequency Range
OSC.
Control
198 Champion Court
Flash-Programmable and 2-Wire Serially
SPI
Q
Φ
P
VDD
VCO
PLL
VSS
Programmable Clock Generator
80 kHz to 200 MHz (3.3V)
80 KHz to 166.6 MHz (2.5V)
80 kHz to 166.6 MHz (3.3V)
80 KHz to 150 MHz (2.5V)
Output Frequency Range
Nonvolatile reprogrammable technology allows easy customi-
zation, quick turnaround on design changes and product perfor-
mance enhancements, and better inventory control. Parts can
be reprogrammed up to 100 times, reducing inventory of
custom parts and providing an easy method for upgrading
existing designs.
The CY22150 can be programmed at the package level.
In-house programming of samples and prototype quantities is
available using the CY3672 FTG Development Kit. Production
quantities are available through Cypress’s value added distri-
bution partners or by using third party programmers from BP
Microsystems‰, HiLo Systems‰, and others.
The CY22150 provides an industry standard interface for
volatile, system level customization of unique frequencies and
options. Serial programming and reprogramming allows quick
design changes and product enhancements, eliminates
inventory of old design parts, and simplifies manufacturing.
High performance suited for commercial, industrial,
networking, telecom, and other general purpose applications.
Application compatibility in standard and low power systems.
Industry standard packaging saves on board space.
AVDD
One-PLL General-Purpose
AVSS
Divider
Bank 1
Divider
Bank 2
San Jose
VDDL
VSSL
,
CA 95134-1709
Crosspoint
Switch
Matrix
Field programmable
Serially programmable
Commercial temperature
Field programmable
Serially programmable
Industrial temperature
Revised January 23, 2009
Specifications
LCLK2
LCLK1
LCKL4
LCLK3
CLK5
CLK6
CY22150
408-943-2600
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CY22150KFZXC Summary of contents

Page 1

... XIN OSC. XOUT Serial SDAT Programming SCLK Interface Cypress Semiconductor Corporation Document #: 38-07104 Rev. *I One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator ■ Nonvolatile reprogrammable technology allows easy customi- zation, quick turnaround on design changes and product perfor- mance enhancements, and better inventory control. Parts can ...

Page 2

Pin Configuration Table 1. Pin Definitions Name Number Description XIN 1 Reference Input. Driven by a crystal (8 MHz to 30 MHz) or external clock (1 MHz to 133 MHz). Programmable input load capacitors allow for maximum flexibility in selecting ...

Page 3

Frequency Calculation and Register Definitions The CY22150 is an extremely flexible clock generator with four basic variables that are used to determine the final output frequency. They are the input reference frequency (REF), the internally calculated P and Q dividers, ...

Page 4

Default Startup Condition for the CY22150 The default (programmed) condition of the device is generally set by the distributor who programs the device using a customer specific JEDEC file produced by CyClocksRT™. Parts shipped from the factory are blank and ...

Page 5

Table 3. Programmable Crystal Input Oscillator Gain Settings Cap Register Settings Effective Load Capacitance (CapLoad) Crystal ESR Crystal Input MHz Frequency MHz MHz MHz Table 4. Bit Locations ...

Page 6

Stable operation of the CY22150 cannot be guaranteed if the value of (P *(REF above 400 MHz or below total total 100 MHz. Registers 40H, 41H, and 42H are defined in PLL Post Divider Options [OCH(7..0)], [47H(7..0)] The ...

Page 7

Table 11. Register 40H Change Pump Bit Settings Address D7 D6 40H 1 1 Although using the above table guarantees stability recom- mended to use the Print Preview function in CyClocksRT to determine the correct charge pump settings ...

Page 8

Table 14. CLKOE Bit Setting Address D7 D6 09H 0 0 Programmable Interface Timing The CY22150 uses a two-wire serial-interface SDAT and SCLK that operates up to 400 kbits/second in Read or Write mode. The basic Write serial format is ...

Page 9

START Figure 6. Frame Format (Device Address, R/W, Register Address, Register Data SDAT + START DA6 DA5DA0 R/W ACK + SCLK Parameter f Frequency of SCLK SCLK Start mode time from SDA LOW to SCL LOW CLK SCLK LOW period ...

Page 10

Applications Controlling Jitter Jitter is defined in many ways including: phase noise, long term jitter, cycle to cycle jitter, period jitter, absolute jitter, and deter- ministic. These jitter terms are usually given in terms of rms, peak to peak, or ...

Page 11

Absolute Maximum Conditions Parameter V Supply Voltage DD V I/O Supply Voltage DDL T Storage Temperature S T Junction Temperature J Package Power Dissipation – Commercial Temp Package Power Dissipation – Industrial Temp Digital Inputs Digital Outputs Referred to V ...

Page 12

AC Electrical Characteristics [7] Parameter Name t1 Output Frequency, Commercial Temp Output Frequency, Industrial Temp t2 Output Duty Cycle LO t2 Output Duty Cycle HI t3 Rising Edge Slew LO Rate (V = 2.5V) DDL t4 Falling Edge Slew LO ...

Page 13

... TSSOP- Tape and Reel [10, 11] CY22150ZXI-xxx 16-Pin TSSOP [10, 11] CY22150ZXI-xxxT 16-Pin TSSOP- Tape and Reel CY22150KFZXC 16-Pin TSSOP CY22150KFZXCT 16-Pin TSSOP - Tape and Reel CY22150KFZXI 16-Pin TSSOP CY22150KFZXIT 16-Pin TSSOP - Tape and Reel [10] CY22150KZXI-xxxT 16-Pin TSSOP- Tape and Reel Programmer ...

Page 14

Package Diagram Figure 11. 16-Pin TSSPO 4.40 mm Body Z16.173 1 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 0.05[0.002] 0.85[0.033] 0.15[0.006] 0.95[0.037] 4.90[0.193] 5.10[0.200] Document #: 38-07104 Rev. *I PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. REFERENCE JEDEC MO-153 6.25[0.246] PACKAGE WEIGHT ...

Page 15

... Added Pb-Free Devices AESA Updated template. Added Note “Not recommended for new designs.” Added part number CY22150KFC, CY22150KFCT, CY22150KFI, CY22150KFZXC, CY22150KFZXCT, CY22150KFZXI, CY22150KFZXIT, CY22150KZXI-xxxT, and CY22150KZI-xxxT in ordering information table. Replaced Lead Free with Pb-Free. following parts: CY22150KFC, CY22150KFCT, CY22150KFI Added CY22150KZI-xxx to the Ordering Information Table ...

Page 16

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

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