CY2308SXC-1 Cypress Semiconductor Corp, CY2308SXC-1 Datasheet

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CY2308SXC-1

Manufacturer Part Number
CY2308SXC-1
Description
IC CLK ZDB 8OUT 133MHZ 16SOIC
Manufacturer
Cypress Semiconductor Corp
Type
Fanout Distribution, Zero Delay Bufferr
Datasheet

Specifications of CY2308SXC-1

Number Of Circuits
1
Package / Case
16-SOIC (3.9mm Width)
Pll
Yes with Bypass
Input
LVCMOS, LVTTL
Output
LVCMOS
Ratio - Input:output
1:8
Differential - Input:output
No/No
Frequency - Max
133.3MHz
Divider/multiplier
No/No
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Frequency-max
133MHz
Output Frequency Range
10 MHz to 133.3 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-1768-5
CY2308SXC-1

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Features
Functional Description
The CY2308 is a 3.3 V Zero Delay Buffer designed to distribute
high speed clocks in PC, workstation, datacom, telecom, and
other high performance applications.
The part has an on-chip PLL that locks to an input clock
presented on the REF pin. The PLL feedback is driven from
external FBK pin, so user has flexibility to choose any one of the
outputs as feedback input and connect it to FBK pin. The
input-to-output skew is less than 250 ps and output-to-output
skew is less than 200 ps.
Cypress Semiconductor Corporation
Document Number: 38-07146 Rev. *L
Logic Block Diagram
Zero input-output propagation delay, adjustable by capacitive
load on FBK input
Multiple configurations, see
on page 4
Multiple low skew outputs
Two banks of four outputs, three-stateable by two select inputs
10 MHz to 133 MHz operating range
75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
Space saving 16-pin 150 mil SOIC package or 16-pin TSSOP
3.3 V operation
Industrial temperature available
for more details
REF
Available CY2308 Configurations
Extra Divider (–5H)
S2
S1
/2
Extra Divider (–3, –4)
/2
Extra Divider (–2, –3)
Select Input
198 Champion Court
Decoding
PLL
MUX
The CY2308 has two banks of four outputs each that is controlled
by the select inputs as shown in the table
on page 3.
three-stated. The input clock is directly applied to the output for
chip and system testing purposes by the select inputs.
The CY2308 PLL enters a power down state when there are no
rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off resulting in less than 25 A
of current draw. The PLL shuts down in two additional cases as
shown in the table
Multiple CY2308 devices accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is less than 700 ps.
The CY2308 is available in five different configurations as shown
in the table
The CY2308–1 is the base part where the output frequencies
equal the reference if there is no counter in the feedback path.
The CY2308–1H is the high drive version of the –1 and rise
and fall times on this device are much faster.
The CY2308–2 enables the user to obtain 2x and 1x
frequencies on each output bank. The exact configuration and
output frequencies depend on the user’s selection of output
that drives the feedback pin.
The CY2308–3 enables the user to obtain 4x and 2x
frequencies on the outputs.
The CY2308–4 enables the user to obtain 2x clocks on all
outputs. Thus, the part is extremely versatile and is used in a
variety of applications.
The CY2308–5H is a high drive version with REF/2 on both
banks.
/2
Available CY2308 Configurations on page
San Jose
If all output clocks are not required, Bank B is
3.3 V Zero Delay Buffer
Select Input Decoding on page
,
CA 95134-1709
FBK
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Revised October 11, 2010
Select Input Decoding
408-943-2600
3.
CY2308
4.
[+] Feedback

Related parts for CY2308SXC-1

CY2308SXC-1 Summary of contents

Page 1

... Logic Block Diagram REF /2 Extra Divider (–5H Cypress Semiconductor Corporation Document Number: 38-07146 Rev. *L The CY2308 has two banks of four outputs each that is controlled by the select inputs as shown in the table on page 3. three-stated. The input clock is directly applied to the output for chip and system testing purposes by the select inputs. ...

Page 2

Contents Features ............................................................................. 1 Functional Description ..................................................... 1 Pinouts .............................................................................. 3 Select Input Decoding ...................................................... 3 Zero Delay and Skew Control .......................................... 4 Available CY2308 Configurations ................................... 4 Maximum Ratings ............................................................. 5 Operating Conditions for Commercial Temperature Devices .................................. 5 ...

Page 3

Pinouts Table 1. Pin Definitions - 16 Pin SOIC Pin Signal [1] 1 REF [2] 2 CLKA1 [2] 3 CLKA2 GND [2] 6 CLKB1 [2] 7 CLKB2 [ [ [2] 10 CLKB3 ...

Page 4

Available CY2308 Configurations Device Feedback From CY2308–1 Bank A or Bank B CY2308–1H Bank A or Bank B CY2308–2 Bank A CY2308–2 Bank B CY2308–3 Bank A CY2308–3 Bank B CY2308–4 Bank A or Bank B CY2308–5H Bank A or ...

Page 5

Maximum Ratings Supply voltage to ground potential ...............–0 +7 input voltage (except REF) ............ –0 input voltage REF ........................................–0 Storage temperature................................. –65 °C to +150 °C Operating Conditions ...

Page 6

Switching Characteristics for Commercial Temperature Devices [9] Parameter Name [10, 12] t Duty cycle = (–1, –2, –3, –4, –1H, –5H) [10, 12] t Duty cycle = (–1, –2, –3, –4, –1H, –5H) [10, ...

Page 7

Operating Conditions for Industrial Temperature Devices Parameter V Supply voltage DD T Operating temperature (ambient temperature Load capacitance, below 100 MHz L Load capacitance, from 100 MHz to 133 MHz [13] C Input capacitance IN t Power up ...

Page 8

Switching Characteristics for Industrial Temperature Devices [15] Parameter Name [16, 17] t Rise time 3 (–1H, –5H) [16, 17] t Fall time 4 (–1, –2, –3, –4) [16, 17] t Fall time 4 (–1, –2, –3, –4) [16, 17] t ...

Page 9

Switching Waveforms OUTPUT 1.4V OUTPUT OUTPUT INPUT FBK FBK, Device 1 FBK, Device 2 Document Number: 38-07146 Rev. *L Figure 3. Duty Cycle Timing 1.4V 1.4V 1.4V Figure 4. All Outputs Rise/Fall Time 2.0V 2.0V 0.8V ...

Page 10

Typical Duty Cycle and I [18] DD Duty Cycle Vs VDD (for 30 pF Loads over Frequency - 3.3V, 25C 3.1 3.2 3.3 3.4 3.5 VDD (V) Duty ...

Page 11

Typical Duty Cycle and I [20] DD Duty Cycle Vs VDD (for 30 pF Loads over Frequency - 3.3V, 25C 3.1 3.2 3.3 3.4 3.5 VDD (V) Duty ...

Page 12

Test Circuits Test Circuit 0.1 F Outputs V DD 0.1 F GND GND Test Circuit for all parameters except t Ordering Information Ordering Code [22] CY2308SI–1T 16-pin 150 mil SOIC – Tape and Reel [22] CY2308SI–1H 16-pin ...

Page 13

... SOIC – Tape and Reel CY2308SXI–2 16-pin 150 mil SOIC CY2308SXI–2T 16-pin 150 mil SOIC – Tape and Reel CY2308SXC–3 16-pin 150 mil SOIC CY2308SXC–3T 16-pin 150 mil SOIC – Tape and Reel CY2308SXI–3 16-pin 150 mil SOIC CY2308SXI– ...

Page 14

Package Drawings and Dimensions Figure 9. 16-Pin TSSOP 4.40 mm Body Z16.173 Document Number: 38-07146 Rev. *L Figure 8. 16-Pin (150 Mil) SOIC S16.15 CY2308 51-85068 *C 51-85091 *C Page [+] Feedback ...

Page 15

Acronyms Table 2. Acronyms Used in this Document Acronym Description FBK Feedback PLL Phase locked loop MUX Multiplexer Document Conventions Units of Measure Table 3. Units of Measure Symbol Unit of Measure °C degrees Celsius dB decibels fC femtoCoulomb fF ...

Page 16

Document History Page Document Title: CY2308 3.3V Zero Delay Buffer Document Number: 38-07146 Orig. of Submission Rev. ECN Change Date ** 110255 SZV 12/17/01 *A 118722 RGL 10/31/02 *B 121832 RBI 12/14/02 *C 235854 RGL 06/24/04 *D 310594 RGL 02/09/05 ...

Page 17

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

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