CY2077FS Cypress Semiconductor Corp, CY2077FS Datasheet - Page 5

• Manufacturer Part Number: CY2077FS
• Description: IC CLOCK GEN PROG 8-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Generatorr

Specifications of CY2077FS

• Pll: Yes
• Input: Clock, Crystal
• Output: CMOS, TTL
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/No
• Frequency - Max: 100MHz, 133MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.3V, 5V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Output Clock Switching Characteristics Commercial
Over the Operating Range
Document Number: 38-07210 Rev. *D
Notes
t
t
t
t
t
t
t
t
t
t
t
t
t
4. Not all parameters measured in production testing.
5. Oscillator start time can not be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70Ω.
1w
1x
1y
2
3
4
5a
5b
6
7a
7b
8
9
Parameter
Output duty cycle at 1.4V, V
= 4.5 – 5.5V
t
Output duty cycle at V
= 4.5 – 5.5V
t
Output duty cycle at V
= 3.0 – 3.6V
t
Output clock rise time
Output clock fall time
Startup time out of power down PWR_DWN pin LOW to HIGH
Power down delay time
(synchronous setting)
Power down delay time
(asynchronous setting)
Power up time
Output disable time
(synchronous setting)
Output disable time
(asynchronous setting)
Output enable time
(always synchronous
enable)
Peak-to-peak period jitter
1w
1x
1y
= t
= t
= t
1A
1A
1A
÷ t
÷ t
÷ t
Description
1B
1B
1B
[4]
DD
DD
/2, V
/2, V
DD
DD
DD
1 – 40 MHz, C
40 – 125 MHz, C
125 – 133 MHz, C
1 – 40 MHz, C
40 – 125 MHz, C
125 – 133 MHz, C
1 – 40 MHz, C
40 – 100 MHz, C
Between 0.8 – 2.0V, V
Between 0.8 – 2.0V, V
Between 0.8 – 2.0V, V
Between 0.2V
Between 0.2V
Between 0.2V
Between 0.8V –2.0V, V
Between 0.8 – 2.0V, V
Between 0.8 – 2.0V, V
Between 0.2V
Between 0.2V
Between 0.2V
PWR_DWN pin LOW to output LOW
(T= period of output CLK)
PWR_DWN pin LOW to output LOW
From power on
OE pin LOW to output high-Z
(T= period of output CLK)
OE pin LOW to output high-Z
OE pin LOW to HIGH
(T= period of output CLK)
V
V
DD
DD
= 3.0V – 3.6V, 4.5V – 5.5V, Fo > 33 MHz, V
= 3.0V – 5.5V, Fo < 33 MHz
DD
DD
DD
DD
DD
DD
L
L
L
[5]
<= 50 pF
<= 50 pF
<= 30 pF
L
L
L
– 0.8V
– 0.8V
– 0.8V
– 0.8V
– 0.8V
– 0.8V
L
L
<= 25 pF
<= 25 pF
<= 15 pF
<= 15 pF
<= 15 pF
Test Conditions
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
= 4.5V – 5.5V, C
= 4.5V – 5.5V, C
= 4.5V – 5.5V, C
= 4.5V – 5.5V, C
= 4.5V – 5.5V, C
, V
, V
, V
= 4.5V – 5.5V, C
, V
, V
, V
DD
DD
DD
DD
DD
DD
[5]
= 4.5V – 5.5V, C
= 3.0V – 3.6V, C
= 3.0V – 3.6V, C
= 4.5V – 5.5V, C
= 3.0V – 3.6V, C
= 3.0V – 3.6V, C
L
L
L
L
L
L
= 50 pF
= 25 pF
= 15 pF
= 25 pF
= 15 pF
= 50 pF
CO
L
L
L
L
L
L
> 100 MHz
= 50 pF
= 30 pF
= 15 pF
= 50 pF
= 30 pF
= 15 pF
Min
45
45
45
45
45
45
45
40
0.3%
Typ Max Unit
T/2
T/2
10
10
80
1
1
T
CY2077
Page 5 of 14
1.5T
25n
150
T +
T +
1%
1.8
1.2
0.9
3.4
4.0
2.4
1.8
1.2
0.9
3.4
4.0
2.4
15
55
55
55
55
55
55
55
60
10
15
10
2
2
+
s
% of
ms
ms
F
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
%
%
%
%
%
%
%
%
O
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