ICS9DB202CK-01LFT IDT, Integrated Device Technology Inc, ICS9DB202CK-01LFT Datasheet - Page 7

• Manufacturer Part Number: ICS9DB202CK-01LFT
• Description: IC JITTER ATTENUATOR 32-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Jitter Attenuatorr

Specifications of ICS9DB202CK-01LFT

• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: HCSL
• Frequency - Max: 140MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN
• Frequency-max: 140MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9DB202CK-01LFT

D
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the V
and V
examples for the HiPerClockS CLK/nCLK input driven by the
most common driver types. The input interfaces suggested here
are examples only. Please consult with the vendor of the driver
F
IDT
F
F
IGURE
IGURE
IGURE
IFFERENTIAL
ICS9DB202-01
PCI EXPRESS JITTER ATTENUATOR
™
2.5V
/ ICS
CMR
HCSL
3.3V
3A. H
3C. H
3E. H
*Optional – R3 and R4 can be 0Ω
™
input requirements. Figures 4A to 4F show interface
1.8V
PCI EXPRESS JITTER ATTENUATOR
LVPECL
D
D
H
D
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
I
RIVEN BY A
I
RIVEN BY AN
I
*R3
*R4
I
RIVEN BY A
P
P
P
P
C
ER
ER
ER
ER
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
C
C
C
C
33
33
Zo = 50 Ohm
Zo = 50 Ohm
LOCK
LOCK
LOCK
LOCK
I
NPUT
3.3V LVPECL D
3.3V HCSL D
S CLK/nCLK I
S CLK/nCLK I
S LVHSTL D
S CLK/nCLK I
IDT O
Zo = 50Ω
Zo = 50Ω
I
NTERFACE
R1
50
3.3V
R3
125
PEN
R1
84
R1
50
E
R2
50
R4
125
MITTER
RIVER
R2
84
RIVER
NPUT
NPUT
NPUT
RIVER
CLK
nCLK
R2
50
CLK
nCLK
3.3V
3.3V
CLK
nCLK
HiPerClockS
Input
HiPerClockS
Input
3.3V
HiPerClockS
Input
PP
7
component to confirm the driver termination requirements. For
example in Figure 4A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
F
F
F
IGURE
IGURE
IGURE
2.5V
3.3V
3.3V
3B. H
3D. H
3F. H
SSTL
LVDS_Driv er
LVPECL
D
D
D
I
RIVEN BY A
I
RIVEN BY A
I
RIVEN BY A
P
P
P
ER
ER
ER
Zo = 50 Ohm
Zo = 50 Ohm
C
C
Zo = 60Ω
Zo = 60Ω
C
ICS9DB202CK-01 REV. B FEBRUARY 18, 2009
LOCK
LOCK
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
3.3V LVPECL D
2.5V SSTL D
3.3V LVDS D
S CLK/nCLK I
S CLK/nCLK I
S CLK/nCLK I
R1
50
R3
120
R3
50
2.5V
R1
120
R2
50
R1
100
R4
120
RIVER
RIVER
CLK
nCLK
R2
120
NPUT
NPUT
NPUT
3.3V
RIVER
HiPerClockS
Input
CLK
nCLK
CLK
nCLK
3.3V
3.3V
HiPerClockS
Receiv er