LMX2335TM National Semiconductor, LMX2335TM Datasheet - Page 11

• Manufacturer Part Number: LMX2335TM
• Description: IC FREQ SYNTHESIZER DUAL 16TSSOP
• Manufacturer: National Semiconductor
• Series: PLLatinum™r
• Type: PLL Frequency Synthesizerr

Specifications of LMX2335TM

• Pll: Yes with Bypass
• Input: CMOS, TTL
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: No/No
• Frequency - Max: 1.1GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 1.1GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *LMX2335TM

Functional Description
(Continued)
Note 9: When the F
LD output is disabled it is actively pulled to a low logic state.
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Note 10: Lock detect output provided to indicate when the VCO frequency is in “lock”. When the loop is locked and a lock detect mode is selected, the pins output
is HIGH, with narrow pulses LOW. In the RF1/RF2 lock detect mode a locked condition is indicated when RF2 and RF1 are both locked.
Note 11: The Fastlock mode utilized the F
LD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock
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occurs whenever the RF loop’s Icpo magnitude bit # 17 is selected HIGH (while the # 19 and # 20 mode bits are set for Fastlock).
Note 12: The Counter Reset mode bits R19 and R20 when activated reset all counters. Upon removal of the Reset bits the N counter resumes counting in “close”
alignment with the R counter. (The maximum error is one prescaler cycle). If the Reset bits are activated the R counter is also forced to Reset, allowing smooth ac-
quisition upon powering up.
SERIAL DATA INPUT TIMING
DS012332-8
Notes: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around V
/2. The test waveform has an edge rate of 0.6V/ns with
CC
amplitudes of 2.2V
@
V
= 2.7V and 2.6V
@
V
= 5.5V.
CC
CC
PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
DS012332-9
Notes: Phase difference detection range: −2 to +2
The minimum width pump up and pump down current pulses occur at the D
pin when the loop is locked.
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